------------------------------------------------------------------------------- -- Copyright Intel Corporation 2004 -- **************************************************************************** -- Intel Corporation makes no warranty for the use of its products -- and assumes no responsibility for any errors which may appear in -- this document nor does it make a commitment to update the information -- contained herein. -- **************************************************************************** -- Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto -- standard means of describing essential features of ANSI/IEEE 1149.1-1994 -- compliant devices. **************************************************************************** -- This file supports the Intel(r) IXP28XX Product Line of Network Processors. -- -------------------------------------------------------------------------- -- Rev: 1.1 11/19/04 - The older IXP2800_B0 was replaced with this new BSDL. -------------------------------------------------------------------------- entity IXP2800_B1 is generic(Physical_Pin_Map : string := "bga_1356"); port( FC_RXCDAT_3 : in bit; QDR1_Q_H_2 : inout bit; QDR1_Q_H_3 : inout bit; QDR1_Q_H_4 : inout bit; QDR1_Q_H_5 : inout bit; QDR1_Q_H_6 : inout bit; QDR1_Q_H_7 : inout bit; QDR1_Q_H_8 : inout bit; QDR1_Q_H_9 : inout bit; qdr1_WPS_L_0 : out bit; qdr1_WPS_L_1 : out bit; QDR1_Q_H_10 : inout bit; QDR1_Q_H_11 : inout bit; QDR1_Q_H_12 : inout bit; QDR1_Q_H_13 : inout bit; QDR1_Q_H_14 : inout bit; QDR1_Q_H_15 : inout bit; QDR1_Q_H_16 : inout bit; QDR1_Q_H_17 : inout bit; SPI4_RPROT : in bit; qdr3_A_H_10 : out bit; SPI4_TPAR_L : out bit; qdr3_A_H_11 : out bit; qdr3_A_H_12 : out bit; qdr3_A_H_13 : out bit; qdr3_A_H_14 : out bit; qdr3_A_H_15 : out bit; PCI_M66EN : inout bit; qdr3_A_H_16 : out bit; qdr3_A_H_17 : out bit; qdr3_A_H_18 : out bit; qdr3_A_H_19 : out bit; RDR2_CTMN : in bit; SPI4_TCLK : out bit; SR_TX : inout bit; TEST_SCAN_EN : in bit; RDR2_CTM : in bit; RDR2_DQA_0 : inout bit; PCI_PAR : inout bit; RDR2_DQA_1 : inout bit; RDR2_DQA_2 : inout bit; RDR2_DQA_3 : inout bit; qdr1_D_H_10 : out bit; qdr3_A_H_20 : out bit; RDR2_DQA_4 : inout bit; qdr1_D_H_11 : out bit; qdr3_A_H_21 : out bit; RDR2_DQA_5 : inout bit; qdr1_D_H_12 : out bit; qdr3_A_H_22 : out bit; RDR2_DQA_6 : inout bit; qdr1_D_H_13 : out bit; qdr3_A_H_23 : out bit; RDR2_DQA_7 : inout bit; qdr1_RPS_L_0 : out bit; qdr1_D_H_14 : out bit; RDR2_DQA_8 : inout bit; qdr1_RPS_L_1 : out bit; qdr1_D_H_15 : out bit; qdr1_D_H_16 : out bit; qdr1_D_H_17 : out bit; CLK_NRESET : in bit; qdr1_A_H_0 : out bit; qdr1_A_H_1 : out bit; qdr1_A_H_2 : out bit; qdr1_A_H_3 : out bit; qdr1_A_H_4 : out bit; qdr1_A_H_5 : out bit; qdr1_A_H_6 : out bit; qdr1_A_H_7 : out bit; qdr1_A_H_8 : out bit; qdr1_A_H_9 : out bit; FC_TXCPAR : out bit; CLK_PHASE_REF : inout bit; PCI_TRDY_L : inout bit; qdr0_ZQ_0 : out bit; qdr0_ZQ_1 : out bit; SPI4_RCTL : in bit; CLK_REF_CLK_H : in bit; CLK_REF_CLK_L : in bit; RDR2_DQB_0 : inout bit; RDR2_DQB_1 : inout bit; RDR2_DQB_2 : inout bit; RDR2_DQB_3 : inout bit; VCC33 : linkage bit_vector (0 to 3); RDR2_DQB_4 : inout bit; RDR2_DQB_5 : inout bit; RDR2_DQB_6 : inout bit; RDR2_DQB_7 : inout bit; RDR2_DQB_8 : inout bit; qdr0_C_H_0 : out bit; RDR1_PCLKM : in bit; VCCRA : linkage bit_vector(0 to 5); qdr0_C_H_1 : out bit; PAS0_VCCA : linkage bit; qdr0_K_H_0 : out bit; qdr0_K_H_1 : out bit; JTAG_TMS : in bit; qdr1_BWS_L_0 : out bit; RDR2_CFMN : in bit; qdr1_BWS_L_1 : out bit; PCI_RST_L : inout bit; SP_ALE_L : inout bit; CLK_NRESET_OUT : out bit; TEST_DIODE_A : linkage bit; TEST_DIODE_C : linkage bit; QDR1_CIN_H_0 : inout bit; QDR1_CIN_H_1 : inout bit; SPI4_TCLK_REF : in bit; QDR0_CIN_L_0 : inout bit; SPI4_RDAT_10 : in bit; QDR0_CIN_L_1 : inout bit; SPI4_RDAT_11 : in bit; SPI4_RDAT_12 : in bit; SPI4_RDAT_13 : in bit; SPI4_RDAT_14 : in bit; SPI4_RDAT_15 : in bit; PCI_ZQ1 : inout bit; PCI_ZQ2 : inout bit; FC_RXCFC : out bit; QDR2_Q_H_0 : inout bit; QDR2_Q_H_1 : inout bit; SP_OE_L : inout bit; QDR2_Q_H_2 : inout bit; PCI_SERR_L : inout bit; QDR2_Q_H_3 : inout bit; QDR2_Q_H_4 : inout bit; QDR2_Q_H_5 : inout bit; QDR2_Q_H_6 : inout bit; QDR2_Q_H_7 : inout bit; SPI4_TDAT_L_0 : out bit; QDR2_Q_H_8 : inout bit; SPI4_TDAT_L_1 : out bit; QDR2_Q_H_9 : inout bit; SPI4_TDAT_L_2 : out bit; FC_RXCFC_L : out bit; SPI4_TDAT_L_3 : out bit; SPI4_TDAT_L_4 : out bit; SPI4_TDAT_L_5 : out bit; SPI4_TDAT_L_6 : out bit; SPI4_TDAT_L_7 : out bit; SPI4_TDAT_L_8 : out bit; SPI4_TDAT_L_9 : out bit; VREFHI : linkage bit_vector(0 to 1); PCI_AD_0 : inout bit; QDR2_Q_H_10 : inout bit; PCI_AD_1 : inout bit; QDR2_Q_H_11 : inout bit; PCI_AD_2 : inout bit; QDR2_Q_H_12 : inout bit; SP_CS_L_0 : inout bit; PCI_AD_3 : inout bit; QDR2_Q_H_13 : inout bit; SP_CS_L_1 : inout bit; PCI_AD_4 : inout bit; QDR2_Q_H_14 : inout bit; PCI_AD_5 : inout bit; QDR2_Q_H_15 : inout bit; PCI_AD_6 : inout bit; QDR2_Q_H_16 : inout bit; PCI_AD_7 : inout bit; QDR2_Q_H_17 : inout bit; PCI_AD_8 : inout bit; PCI_REQ64_L : inout bit; PCI_AD_9 : inout bit; SPI4_RSCLK : in bit; VREF_QDR0 : linkage bit_vector (0 to 1); VREF_QDR1 : linkage bit_vector (0 to 1); FC_TXCDAT_L_0 : out bit; VREF_QDR2 : linkage bit_vector (0 to 1); FC_TXCDAT_L_1 : out bit; qdr2_WPS_L_0 : out bit; VREF_QDR3 : linkage bit_vector (0 to 1); FC_TXCDAT_L_2 : out bit; qdr2_WPS_L_1 : out bit; FC_TXCDAT_L_3 : out bit; qdr2_A_H_0 : out bit; qdr0_D_H_0 : out bit; qdr2_A_H_1 : out bit; PCI_FRAME_L : inout bit; qdr0_D_H_1 : out bit; qdr1_ZQ_0 : out bit; qdr2_A_H_2 : out bit; qdr0_D_H_2 : out bit; qdr1_ZQ_1 : out bit; qdr2_A_H_3 : out bit; qdr0_D_H_3 : out bit; qdr2_A_H_4 : out bit; qdr0_D_H_4 : out bit; qdr2_A_H_5 : out bit; qdr0_D_H_5 : out bit; qdr2_A_H_6 : out bit; qdr0_D_H_6 : out bit; qdr2_A_H_7 : out bit; qdr0_D_H_7 : out bit; qdr2_A_H_8 : out bit; qdr0_D_H_8 : out bit; qdr2_A_H_9 : out bit; RDR0_SCK : inout bit; SPI4_TPROT : out bit; qdr0_D_H_9 : out bit; VCC25V : linkage bit_vector (0 to 27); GPIO_0 : inout bit; SPI4_TSTAT_0 : out bit; GPIO_1 : inout bit; SPI4_TSTAT_1 : out bit; GPIO_2 : inout bit; GPIO_3 : inout bit; GPIO_4 : inout bit; GPIO_5 : inout bit; qdr2_D_H_10 : out bit; GPIO_6 : inout bit; qdr2_D_H_11 : out bit; GPIO_7 : inout bit; qdr2_D_H_12 : out bit; qdr2_D_H_13 : out bit; qdr2_D_H_14 : out bit; qdr2_D_H_15 : out bit; qdr2_D_H_16 : out bit; qdr2_D_H_17 : out bit; FC_RXCCLK : in bit; PAS1_VCCA : linkage bit; SPI4_RCLK_REF_L : out bit; SP_CP : inout bit; SPI4_TCTL : out bit; SPI4_RDAT_0 : in bit; SPI4_RDAT_1 : in bit; SPI4_RDAT_2 : in bit; SPI4_RDAT_3 : in bit; SPI4_RDAT_4 : in bit; SPI4_RDAT_5 : in bit; SPI4_RDAT_6 : in bit; SPI4_RDAT_7 : in bit; SPI4_RDAT_8 : in bit; SPI4_RDAT_9 : in bit; VSS_PLL : linkage bit; qdr2_RPS_L_0 : out bit; qdr2_RPS_L_1 : out bit; qdr1_C_H_0 : out bit; RDR2_PCLKM : in bit; qdr1_C_H_1 : out bit; RDR0_SCLKN : in bit; JTAG_TRST : in bit; SPI4_RPAR : in bit; qdr1_K_H_0 : out bit; qdr1_K_H_1 : out bit; PCI_GNT_L_0 : inout bit; PCI_GNT_L_1 : inout bit; FC_RXCSOF_L : in bit; RDR0_CFM : in bit; VREFLO : linkage bit_vector (0 to 1); FC_RXCCLK_L : in bit; qdr0_A_H_10 : out bit; PCI_IRDY_L : inout bit; qdr0_A_H_11 : out bit; QDR3_Q_H_0 : inout bit; qdr0_A_H_12 : out bit; QDR3_Q_H_1 : inout bit; qdr0_A_H_13 : out bit; QDR3_Q_H_2 : inout bit; qdr0_A_H_14 : out bit; QDR3_Q_H_3 : inout bit; qdr0_A_H_15 : out bit; QDR3_Q_H_4 : inout bit; qdr0_A_H_16 : out bit; QDR3_Q_H_5 : inout bit; qdr0_A_H_17 : out bit; QDR3_Q_H_6 : inout bit; qdr0_A_H_18 : out bit; FC_RXCSRB_L : in bit; QDR3_Q_H_7 : inout bit; qdr0_A_H_19 : out bit; QDR3_Q_H_8 : inout bit; QDR3_Q_H_9 : inout bit; qdr0_C_L_0 : out bit; qdr0_C_L_1 : out bit; RDR1_SCK : inout bit; PAR0_PADVREFA : linkage bit; qdr0_K_L_0 : out bit; PAR0_PADVREFB : linkage bit; qdr0_K_L_1 : out bit; FC_RXCSOF : in bit; qdr2_BWS_L_0 : out bit; qdr2_BWS_L_1 : out bit; qdr0_A_H_20 : out bit; qdr0_A_H_21 : out bit; qdr0_A_H_22 : out bit; qdr0_A_H_23 : out bit; FC_RXCPAR_L : in bit; SP_RD_L : inout bit; QDR2_CIN_H_0 : inout bit; QDR2_CIN_H_1 : inout bit; QDR1_CIN_L_0 : inout bit; QDR1_CIN_L_1 : inout bit; qdr2_ZQ_0 : out bit; qdr2_ZQ_1 : out bit; FC_TXCDAT_0 : out bit; FC_TXCDAT_1 : out bit; FC_TXCFC : in bit; FC_TXCDAT_2 : out bit; FC_TXCDAT_3 : out bit; PCI_DEVSEL_L : inout bit; qdr3_A_H_0 : out bit; QDR3_Q_H_10 : inout bit; qdr3_A_H_1 : out bit; qdr1_D_H_0 : out bit; PAS2_VCCA : linkage bit; QDR3_Q_H_11 : inout bit; qdr3_A_H_2 : out bit; qdr1_D_H_1 : out bit; QDR3_Q_H_12 : inout bit; qdr3_A_H_3 : out bit; qdr1_D_H_2 : out bit; QDR3_Q_H_13 : inout bit; qdr3_A_H_4 : out bit; qdr1_D_H_3 : out bit; QDR3_Q_H_14 : inout bit; qdr3_A_H_5 : out bit; qdr1_D_H_4 : out bit; QDR3_Q_H_15 : inout bit; qdr3_A_H_6 : out bit; qdr1_D_H_5 : out bit; SPI4_TDAT_L_10 : out bit; QDR3_Q_H_16 : inout bit; qdr3_A_H_7 : out bit; qdr1_D_H_6 : out bit; SPI4_TDAT_L_11 : out bit; QDR3_Q_H_17 : inout bit; qdr3_A_H_8 : out bit; qdr1_D_H_7 : out bit; SPI4_TDAT_L_12 : out bit; qdr3_A_H_9 : out bit; qdr1_D_H_8 : out bit; SPI4_TDAT_L_13 : out bit; qdr1_D_H_9 : out bit; SPI4_TDAT_L_14 : out bit; SPI4_TDAT_L_15 : out bit; VCCA_SPI4 : linkage bit; RDR0_SIO : inout bit; RDR1_CFM : in bit; FC_RXCSRB : in bit; VREFHI_CLK : linkage bit; SPI4_RCTL_L : in bit; SPI4_TSCLK : out bit; qdr3_D_H_10 : out bit; qdr3_D_H_11 : out bit; qdr3_D_H_12 : out bit; qdr3_D_H_13 : out bit; qdr3_D_H_14 : out bit; RDR0_RQ_0 : inout bit; qdr3_D_H_15 : out bit; RDR0_RQ_1 : inout bit; qdr3_D_H_16 : out bit; RDR0_RQ_2 : inout bit; qdr3_D_H_17 : out bit; RDR0_RQ_3 : inout bit; RDR0_RQ_4 : inout bit; qdr3_WPS_L_0 : out bit; RDR0_RQ_5 : inout bit; qdr3_WPS_L_1 : out bit; RDR0_RQ_6 : inout bit; RDR0_RQ_7 : inout bit; qdr2_C_H_0 : out bit; qdr2_C_H_1 : out bit; RDR1_SCLKN : in bit; SPI4_TPAR : out bit; qdr2_K_H_0 : out bit; RDR2_SCK : inout bit; qdr2_K_H_1 : out bit; SPI4_RPROT_L : in bit; SPI4_TDAT_10 : out bit; SPI4_TDAT_11 : out bit; SPI4_TDAT_12 : out bit; SPI4_TDAT_13 : out bit; SPI4_TDAT_14 : out bit; SPI4_TDAT_15 : out bit; TEST_SCAN_CLK_A : in bit; TEST_SCAN_CLK_B : in bit; CLK_CFG_RST_DIR : in bit; qdr3_RPS_L_0 : out bit; qdr3_RPS_L_1 : out bit; FC_TXCFC_L : in bit; RDR0_CMD : inout bit; FC_PREEMP : inout bit; qdr3_ZQ_0 : out bit; qdr3_ZQ_1 : out bit; qdr1_C_L_0 : out bit; PCI_CLK : in bit; qdr1_C_L_1 : out bit; qdr1_K_L_0 : out bit; qdr1_K_L_1 : out bit; qdr1_A_H_10 : out bit; qdr1_A_H_11 : out bit; qdr1_A_H_12 : out bit; qdr1_A_H_13 : out bit; qdr1_A_H_14 : out bit; TEST_MODE_LOAD : in bit; RDR1_SIO : inout bit; qdr1_A_H_15 : out bit; qdr1_A_H_16 : out bit; qdr1_A_H_17 : out bit; qdr1_A_H_18 : out bit; qdr1_A_H_19 : out bit; RDR2_CFM : in bit; FC_TXCCLK : out bit; PAS3_VCCA : linkage bit; SPI4_TDAT_0 : out bit; SPI4_TDAT_1 : out bit; PCI_REQ_L_0 : inout bit; SPI4_TDAT_2 : out bit; PCI_REQ_L_1 : inout bit; SPI4_TDAT_3 : out bit; CLK_STOP : in bit; SPI4_TDAT_4 : out bit; SPI4_TDAT_5 : out bit; qdr1_A_H_20 : out bit; SPI4_TDAT_6 : out bit; qdr1_A_H_21 : out bit; SPI4_TDAT_7 : out bit; qdr1_A_H_22 : out bit; SPI4_TDAT_8 : out bit; qdr1_A_H_23 : out bit; SPI4_TDAT_9 : out bit; SPI4_PREEMP : inout bit; VCCR : linkage bit_vector(0 to 13); qdr2_D_H_0 : out bit; qdr2_D_H_1 : out bit; qdr2_D_H_2 : out bit; qdr2_D_H_3 : out bit; qdr2_D_H_4 : out bit; qdr2_D_H_5 : out bit; qdr2_D_H_6 : out bit; qdr2_D_H_7 : out bit; qdr2_D_H_8 : out bit; qdr2_D_H_9 : out bit; qdr3_BWS_L_0 : out bit; qdr3_BWS_L_1 : out bit; QDR3_CIN_H_0 : inout bit; QDR3_CIN_H_1 : inout bit; RDR1_RQ_0 : inout bit; RDR1_RQ_1 : inout bit; PCI_STOP_L : inout bit; QDR2_CIN_L_0 : inout bit; RDR1_RQ_2 : inout bit; QDR2_CIN_L_1 : inout bit; RDR1_RQ_3 : inout bit; RDR1_RQ_4 : inout bit; RDR1_RQ_5 : inout bit; RDR1_RQ_6 : inout bit; RDR1_RQ_7 : inout bit; SPI4_RCLK_L : in bit; SP_ACK_L : inout bit; PAR1_PADVREFA : linkage bit; RDR0_DQA_0 : inout bit; VCC33_PCI : linkage bit_vector (0 to 11); PAR1_PADVREFB : linkage bit; RDR0_DQA_1 : inout bit; RDR0_DQA_2 : inout bit; RDR0_DQA_3 : inout bit; RDR0_DQA_4 : inout bit; RDR0_DQA_5 : inout bit; RDR0_DQA_6 : inout bit; RDR0_DQA_7 : inout bit; RDR0_DQA_8 : inout bit; VCCA_FC : linkage bit; FC_RXCDAT_L_0 : in bit; FC_RXCDAT_L_1 : in bit; FC_RXCDAT_L_2 : in bit; FC_RXCDAT_L_3 : in bit; PCI_IDSEL : inout bit; RDR1_CMD : inout bit; qdr3_C_H_0 : out bit; qdr3_C_H_1 : out bit; RDR2_SCLKN : in bit; qdr3_K_H_0 : out bit; SPI4_ZQ1 : linkage bit; qdr3_K_H_1 : out bit; SPI4_ZQ2 : linkage bit; PCI_PERR_L : inout bit; SPI4_RPAR_L : in bit; FC_TXCSOF : out bit; RDR2_SIO : inout bit; SPI4_RCLK_REF : out bit; PCI_PAR64 : inout bit; RDR0_CTMN : in bit; VDDQ : linkage bit_vector (0 to 100); RDR0_DQB_0 : inout bit; RDR0_DQB_1 : inout bit; RDR0_DQB_2 : inout bit; RDR0_DQB_3 : inout bit; RDR0_DQB_4 : inout bit; RDR0_DQB_5 : inout bit; RDR0_DQB_6 : inout bit; SPI4_RDAT_L_0 : in bit; RDR0_DQB_7 : inout bit; SPI4_RDAT_L_1 : in bit; RDR0_DQB_8 : inout bit; SPI4_RDAT_L_2 : in bit; SPI4_RDAT_L_3 : in bit; SPI4_RDAT_L_4 : in bit; SPI4_RDAT_L_5 : in bit; qdr0_WPS_L_0 : out bit; SPI4_RDAT_L_6 : in bit; qdr0_WPS_L_1 : out bit; SPI4_RDAT_L_7 : in bit; SPI4_RDAT_L_8 : in bit; SPI4_RDAT_L_9 : in bit; qdr2_C_L_0 : out bit; SP_WR_L : inout bit; SP_AD_0 : inout bit; qdr2_C_L_1 : out bit; SP_AD_1 : inout bit; SP_AD_2 : inout bit; FC_RXCPAR : in bit; SP_AD_3 : inout bit; SP_AD_4 : inout bit; SP_AD_5 : inout bit; SP_AD_6 : inout bit; qdr2_K_L_0 : out bit; SP_AD_7 : inout bit; qdr2_K_L_1 : out bit; PCI_AD_10 : inout bit; PCI_AD_11 : inout bit; PCI_AD_12 : inout bit; VCC_PLL : linkage bit; PCI_AD_13 : inout bit; PCI_AD_14 : inout bit; PCI_AD_15 : inout bit; PCI_AD_16 : inout bit; PCI_AD_17 : inout bit; PCI_AD_18 : inout bit; PCI_AD_19 : inout bit; FC_TXCSOF_L : out bit; VCC_FUSE : linkage bit_vector(0 to 3); QDR0_Q_H_10 : inout bit; QDR0_Q_H_11 : inout bit; QDR0_Q_H_12 : inout bit; QDR0_Q_H_13 : inout bit; QDR0_Q_H_14 : inout bit; QDR0_Q_H_15 : inout bit; QDR0_Q_H_16 : inout bit; QDR0_Q_H_17 : inout bit; RDR0_CTM : in bit; FC_TXCCLK_L : out bit; QDR0_Q_H_0 : inout bit; FC_TXCSRB : out bit; QDR0_Q_H_1 : inout bit; QDR0_Q_H_2 : inout bit; PCI_CBE_L_0 : inout bit; qdr2_A_H_10 : out bit; QDR0_Q_H_3 : inout bit; PCI_CBE_L_1 : inout bit; qdr2_A_H_11 : out bit; SPI4_TCTL_L : out bit; QDR0_Q_H_4 : inout bit; PCI_AD_20 : inout bit; PCI_CBE_L_2 : inout bit; qdr2_A_H_12 : out bit; QDR0_Q_H_5 : inout bit; PCI_AD_21 : inout bit; PCI_CBE_L_3 : inout bit; qdr2_A_H_13 : out bit; QDR0_Q_H_6 : inout bit; PCI_AD_22 : inout bit; PCI_CBE_L_4 : inout bit; qdr2_A_H_14 : out bit; FC_ZQ1 : inout bit; QDR0_Q_H_7 : inout bit; PCI_AD_23 : inout bit; PCI_CBE_L_5 : inout bit; qdr2_A_H_15 : out bit; FC_ZQ2 : inout bit; qdr0_RPS_L_0 : out bit; QDR0_Q_H_8 : inout bit; PCI_AD_24 : inout bit; PCI_CBE_L_6 : inout bit; qdr2_A_H_16 : out bit; qdr0_RPS_L_1 : out bit; QDR0_Q_H_9 : inout bit; PCI_AD_25 : inout bit; PCI_CBE_L_7 : inout bit; qdr2_A_H_17 : out bit; JTAG_TCK : in bit; PCI_AD_26 : inout bit; qdr2_A_H_18 : out bit; PCI_AD_27 : inout bit; qdr2_A_H_19 : out bit; FC_TXCSRB_L : out bit; PCI_AD_28 : inout bit; PCI_AD_29 : inout bit; RDR2_RQ_0 : inout bit; RDR2_RQ_1 : inout bit; RDR2_RQ_2 : inout bit; RDR2_CMD : inout bit; RDR2_RQ_3 : inout bit; RDR2_RQ_4 : inout bit; RDR2_RQ_5 : inout bit; RDR2_RQ_6 : inout bit; RDR2_RQ_7 : inout bit; qdr3_D_H_0 : out bit; qdr3_D_H_1 : out bit; qdr3_D_H_2 : out bit; qdr3_D_H_3 : out bit; qdr3_D_H_4 : out bit; qdr3_D_H_5 : out bit; qdr3_D_H_6 : out bit; qdr3_D_H_7 : out bit; qdr3_D_H_8 : out bit; RDR0_CFMN : in bit; qdr3_D_H_9 : out bit; qdr2_A_H_20 : out bit; qdr0_D_H_10 : out bit; qdr2_A_H_21 : out bit; qdr0_D_H_11 : out bit; PCI_AD_30 : inout bit; qdr2_A_H_22 : out bit; qdr0_D_H_12 : out bit; PCI_AD_31 : inout bit; qdr2_A_H_23 : out bit; qdr0_D_H_13 : out bit; PCI_AD_32 : inout bit; FC_TXCPAR_L : out bit; qdr0_D_H_14 : out bit; PCI_AD_33 : inout bit; JTAG_TDI : in bit; qdr0_D_H_15 : out bit; PCI_AD_34 : inout bit; qdr0_D_H_16 : out bit; PCI_AD_35 : inout bit; qdr0_D_H_17 : out bit; PCI_AD_36 : inout bit; PCI_AD_37 : inout bit; PCI_AD_38 : inout bit; SPI4_RCLK : in bit; PCI_AD_39 : inout bit; JTAG_TDO : out bit; PCI_INTA_L : inout bit; SPI4_TCLK_REF_L : in bit; TEST_CLK : in bit; RDR1_DQA_0 : inout bit; RDR1_DQA_1 : inout bit; RDR1_DQA_2 : inout bit; RDR1_DQA_3 : inout bit; RDR1_DQA_4 : inout bit; SP_DIR : inout bit; RDR1_DQA_5 : inout bit; RDR1_DQA_6 : inout bit; PCI_AD_40 : inout bit; RDR1_DQA_7 : inout bit; PCI_AD_41 : inout bit; RDR1_DQA_8 : inout bit; PCI_AD_42 : inout bit; PCI_AD_43 : inout bit; VREFLO_CLK : linkage bit; PCI_AD_44 : inout bit; PCI_AD_45 : inout bit; PCI_AD_46 : inout bit; RDR1_CTMN : in bit; PCI_AD_47 : inout bit; CLK_PLL_BYP : in bit; PCI_AD_48 : inout bit; PCI_AD_49 : inout bit; qdr0_A_H_0 : out bit; qdr0_A_H_1 : out bit; qdr0_A_H_2 : out bit; qdr0_A_H_3 : out bit; qdr0_A_H_4 : out bit; qdr0_A_H_5 : out bit; qdr0_A_H_6 : out bit; qdr0_A_H_7 : out bit; qdr0_A_H_8 : out bit; qdr0_A_H_9 : out bit; SPI4_RSTAT_0 : in bit; qdr0_BWS_L_0 : out bit; SP_CLK : inout bit; SPI4_RSTAT_1 : in bit; qdr0_BWS_L_1 : out bit; SPI4_TPROT_L : out bit; PCI_AD_50 : inout bit; PCI_AD_51 : inout bit; QDR0_CIN_H_0 : inout bit; PCI_AD_52 : inout bit; QDR0_CIN_H_1 : inout bit; PCI_AD_53 : inout bit; PCI_AD_54 : inout bit; PCI_AD_55 : inout bit; PCI_AD_56 : inout bit; PCI_AD_57 : inout bit; PCI_AD_58 : inout bit; QDR3_CIN_L_0 : inout bit; PCI_AD_59 : inout bit; QDR3_CIN_L_1 : inout bit; PCI_INTB_L : inout bit; RDR1_CTM : in bit; RDR1_DQB_0 : inout bit; RDR1_DQB_1 : inout bit; RDR1_DQB_2 : inout bit; RDR1_DQB_3 : inout bit; RDR1_DQB_4 : inout bit; RDR1_DQB_5 : inout bit; RDR1_DQB_6 : inout bit; RDR1_DQB_7 : inout bit; PCI_AD_60 : inout bit; VCCRIO : linkage bit_vector(0 to 8); RDR1_DQB_8 : inout bit; PCI_AD_61 : inout bit; PCI_AD_62 : inout bit; PCI_AD_63 : inout bit; RDR0_PCLKM : in bit; SPI4_RDAT_L_10 : in bit; VCC_CLK : linkage bit; qdr3_C_L_0 : out bit; SPI4_RDAT_L_11 : in bit; qdr3_C_L_1 : out bit; SPI4_RDAT_L_12 : in bit; SPI4_RDAT_L_13 : in bit; SPI4_RDAT_L_14 : in bit; SPI4_RDAT_L_15 : in bit; PAR2_PADVREFA : linkage bit; qdr3_K_L_0 : out bit; PAR2_PADVREFB : linkage bit; qdr3_K_L_1 : out bit; PCI_ACK64_L : inout bit; SR_RX : inout bit; CLK_RST_DIS : in bit; SPI4_TCLK_L : out bit; RDR1_CFMN : in bit; FC_RXCDAT_0 : in bit; QDR1_Q_H_0 : inout bit; FC_RXCDAT_1 : in bit; QDR1_Q_H_1 : inout bit; FC_RXCDAT_2 : in bit; VSS : linkage bit_vector(0 to 369); VCC : linkage bit_vector(0 to 77) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of IXP2800_B1 : entity is "STD_1149_1_1993"; attribute PIN_MAP of IXP2800_B1 : entity is PHYSICAL_PIN_MAP; constant bga_1356:PIN_MAP_STRING := "FC_RXCDAT_3 : AK5, " & "QDR1_Q_H_2 : AG24, " & "QDR1_Q_H_3 : AJ26, " & "QDR1_Q_H_4 : AL28, " & "QDR1_Q_H_5 : AT30, " & "QDR1_Q_H_6 : AR31, " & "QDR1_Q_H_7 : AK28, " & "QDR1_Q_H_8 : AJ28, " & "QDR1_Q_H_9 : AN30, " & "qdr1_WPS_L_0 : AN21, " & "qdr1_WPS_L_1 : AN20, " & "QDR1_Q_H_10 : AR32, " & "QDR1_Q_H_11 : AR30, " & "QDR1_Q_H_12 : AU31, " & "QDR1_Q_H_13 : AM29, " & "QDR1_Q_H_14 : AK27, " & "QDR1_Q_H_15 : AH27, " & "QDR1_Q_H_16 : AG26, " & "QDR1_Q_H_17 : AH25, " & "SPI4_RPROT : AB12, " & "qdr3_A_H_10 : V35, " & "SPI4_TPAR_L : AB4, " & "qdr3_A_H_11 : V30, " & "qdr3_A_H_12 : Y29, " & "qdr3_A_H_13 : W27, " & "qdr3_A_H_14 : T31, " & "qdr3_A_H_15 : AA35, " & "PCI_M66EN : L12, " & "qdr3_A_H_16 : Y30, " & "qdr3_A_H_17 : Y35, " & "qdr3_A_H_18 : Y27, " & "qdr3_A_H_19 : V27, " & "RDR2_CTMN : A33, " & "SPI4_TCLK : T3, " & "SR_TX : K26, " & "TEST_SCAN_EN : H20, " & "RDR2_CTM : A34, " & "RDR2_DQA_0 : A35, " & "PCI_PAR : J2, " & "RDR2_DQA_1 : C35, " & "RDR2_DQA_2 : E35, " & "RDR2_DQA_3 : A36, " & "qdr1_D_H_10 : AK25, " & "qdr3_A_H_20 : P37, " & "RDR2_DQA_4 : C36, " & "qdr1_D_H_11 : AN27, " & "qdr3_A_H_21 : T37, " & "RDR2_DQA_5 : E36, " & "qdr1_D_H_12 : AU29, " & "qdr3_A_H_22 : R36, " & "RDR2_DQA_6 : D37, " & "qdr1_D_H_13 : AT28, " & "qdr3_A_H_23 : N36, " & "RDR2_DQA_7 : F37, " & "qdr1_RPS_L_0 : AK22, " & "qdr1_D_H_14 : AR26, " & "RDR2_DQA_8 : B37, " & "qdr1_RPS_L_1 : AL22, " & "qdr1_D_H_15 : AN25, " & "qdr1_D_H_16 : AK24, " & "qdr1_D_H_17 : AJ22, " & "CLK_NRESET : L20, " & "qdr1_A_H_0 : AN23, " & "qdr1_A_H_1 : AF21, " & "qdr1_A_H_2 : AT18, " & "qdr1_A_H_3 : AJ20, " & "qdr1_A_H_4 : AG20, " & "qdr1_A_H_5 : AF22, " & "qdr1_A_H_6 : AR20, " & "qdr1_A_H_7 : AR25, " & "qdr1_A_H_8 : AU23, " & "qdr1_A_H_9 : AM21, " & "FC_TXCPAR : AJ7, " & "CLK_PHASE_REF : M29, " & "PCI_TRDY_L : L7, " & "qdr0_ZQ_0 : AK13, " & "qdr0_ZQ_1 : AM12, " & "SPI4_RCTL : AD6, " & "CLK_REF_CLK_H : N28, " & "CLK_REF_CLK_L : N27, " & "RDR2_DQB_0 : E29, " & "RDR2_DQB_1 : C30, " & "RDR2_DQB_2 : E30, " & "RDR2_DQB_3 : C29, " & "VCC33 : (H26, " & "L22, " & "L29, " & "R26), " & "RDR2_DQB_4 : A29, " & "RDR2_DQB_5 : E28, " & "RDR2_DQB_6 : C28, " & "RDR2_DQB_7 : A28, " & "RDR2_DQB_8 : A27, " & "qdr0_C_H_0 : AR13, " & "RDR1_PCLKM : D14, " & "VCCRA : (G5, " & "G19, " & "G22, " & "G30, " & "G34, " & "G9), " & "qdr0_C_H_1 : AU11, " & "PAS0_VCCA : AE15, " & "qdr0_K_H_0 : AF19, " & "qdr0_K_H_1 : AR17, " & "JTAG_TMS : J22, " & "qdr1_BWS_L_0 : AG21, " & "RDR2_CFMN : C33, " & "qdr1_BWS_L_1 : AN22, " & "PCI_RST_L : T8, " & "SP_ALE_L : L25, " & "CLK_NRESET_OUT : L21, " & "TEST_DIODE_A : J29, " & "TEST_DIODE_C : K29, " & "QDR1_CIN_H_0 : AN28, " & "QDR1_CIN_H_1 : AN29, " & "SPI4_TCLK_REF : AD8, " & "QDR0_CIN_L_0 : AR9, " & "SPI4_RDAT_10 : AF4, " & "QDR0_CIN_L_1 : AR8, " & "SPI4_RDAT_11 : AB6, " & "SPI4_RDAT_12 : AD10, " & "SPI4_RDAT_13 : AB8, " & "SPI4_RDAT_14 : AD4, " & "SPI4_RDAT_15 : AC2, " & "PCI_ZQ1 : N8, " & "PCI_ZQ2 : R12, " & "FC_RXCFC : AK1, " & "QDR2_Q_H_0 : AR33, " & "QDR2_Q_H_1 : AR34, " & "SP_OE_L : M27, " & "QDR2_Q_H_2 : AU35, " & "PCI_SERR_L : P8, " & "QDR2_Q_H_3 : AR35, " & "QDR2_Q_H_4 : AN32, " & "QDR2_Q_H_5 : AL31, " & "QDR2_Q_H_6 : AH29, " & "QDR2_Q_H_7 : AG27, " & "SPI4_TDAT_L_0 : AA8, " & "QDR2_Q_H_8 : AF27, " & "SPI4_TDAT_L_1 : U5, " & "QDR2_Q_H_9 : AG28, " & "SPI4_TDAT_L_2 : T6, " & "FC_RXCFC_L : AK2, " & "SPI4_TDAT_L_3 : R2, " & "SPI4_TDAT_L_4 : Y8, " & "SPI4_TDAT_L_5 : V7, " & "SPI4_TDAT_L_6 : V3, " & "SPI4_TDAT_L_7 : V9, " & "SPI4_TDAT_L_8 : Y4, " & "SPI4_TDAT_L_9 : W12, " & "VREFHI : (AC11, " & "AL5), " & "PCI_AD_0 : L9, " & "QDR2_Q_H_10 : AK29, " & "PCI_AD_1 : K6, " & "QDR2_Q_H_11 : AK30, " & "PCI_AD_2 : J12, " & "QDR2_Q_H_12 : AL30, " & "SP_CS_L_0 : M24, " & "PCI_AD_3 : M9, " & "QDR2_Q_H_13 : AM31, " & "SP_CS_L_1 : J20, " & "PCI_AD_4 : N9, " & "QDR2_Q_H_14 : AP35, " & "PCI_AD_5 : K5, " & "QDR2_Q_H_15 : AN31, " & "PCI_AD_6 : P10, " & "QDR2_Q_H_16 : AT36, " & "PCI_AD_7 : M8, " & "QDR2_Q_H_17 : AT34, " & "PCI_AD_8 : J4, " & "PCI_REQ64_L : P12, " & "PCI_AD_9 : H3, " & "SPI4_RSCLK : N2, " & "VREF_QDR0 : (AT2, " & "AU3), " & "VREF_QDR1 : (AT32, " & "AU33), " & "FC_TXCDAT_L_0 : AE11, " & "VREF_QDR2 : (AT37, " & "AU36), " & "FC_TXCDAT_L_1 : AF10, " & "qdr2_WPS_L_0 : AE33, " & "VREF_QDR3 : (H36, " & "H37), " & "FC_TXCDAT_L_2 : AG11, " & "qdr2_WPS_L_1 : AD33, " & "FC_TXCDAT_L_3 : AJ9, " & "qdr2_A_H_0 : AF31, " & "qdr0_D_H_0 : AL11, " & "qdr2_A_H_1 : AG33, " & "PCI_FRAME_L : R8, " & "qdr0_D_H_1 : AU5, " & "qdr1_ZQ_0 : AM23, " & "qdr2_A_H_2 : AH33, " & "qdr0_D_H_2 : AK11, " & "qdr1_ZQ_1 : AL24, " & "qdr2_A_H_3 : AC28, " & "qdr0_D_H_3 : AU7, " & "qdr2_A_H_4 : AK36, " & "qdr0_D_H_4 : AR10, " & "qdr2_A_H_5 : AM36, " & "qdr0_D_H_5 : AN12, " & "qdr2_A_H_6 : AG35, " & "qdr0_D_H_6 : AG16, " & "qdr2_A_H_7 : AE32, " & "qdr0_D_H_7 : AM14, " & "qdr2_A_H_8 : AD35, " & "qdr0_D_H_8 : AG15, " & "qdr2_A_H_9 : AB30, " & "RDR0_SCK : F1, " & "SPI4_TPROT : AA1, " & "qdr0_D_H_9 : AK14, " & "VCC25V : (AA10, " & "AA11, " & "AA6, " & "AB2, " & "AC4, " & "AC8, " & "AD11, " & "AE10, " & "AE2, " & "AE6, " & "AG8, " & "AH4, " & "AH6, " & "AJ2, " & "AL4, " & "AN1, " & "AN5, " & "J13, " & "J17, " & "M13, " & "M18, " & "P1, " & "U1, " & "U3, " & "U7, " & "V11, " & "W5, " & "W9), " & "GPIO_0 : K25, " & "SPI4_TSTAT_0 : P5, " & "GPIO_1 : H27, " & "SPI4_TSTAT_1 : P3, " & "GPIO_2 : J26, " & "GPIO_3 : J21, " & "GPIO_4 : J27, " & "GPIO_5 : K24, " & "qdr2_D_H_10 : AF29, " & "GPIO_6 : L24, " & "qdr2_D_H_11 : AH31, " & "GPIO_7 : H21, " & "qdr2_D_H_12 : AJ33, " & "qdr2_D_H_13 : AJ32, " & "qdr2_D_H_14 : AL35, " & "qdr2_D_H_15 : AN37, " & "qdr2_D_H_16 : AL32, " & "qdr2_D_H_17 : AR37, " & "FC_RXCCLK : AM1, " & "PAS1_VCCA : AE24, " & "SPI4_RCLK_REF_L : Y12, " & "SP_CP : M23, " & "SPI4_TCTL : AA3, " & "SPI4_RDAT_0 : AH2, " & "SPI4_RDAT_1 : AG4, " & "SPI4_RDAT_2 : AE4, " & "SPI4_RDAT_3 : AF6, " & "SPI4_RDAT_4 : AG2, " & "SPI4_RDAT_5 : AF2, " & "SPI4_RDAT_6 : AE8, " & "SPI4_RDAT_7 : AD2, " & "SPI4_RDAT_8 : AF8, " & "SPI4_RDAT_9 : AG6, " & "VSS_PLL : N25, " & "qdr2_RPS_L_0 : AD30, " & "qdr2_RPS_L_1 : AD29, " & "qdr1_C_H_0 : AT24, " & "RDR2_PCLKM : D27, " & "qdr1_C_H_1 : AU25, " & "RDR0_SCLKN : F2, " & "JTAG_TRST : K21, " & "SPI4_RPAR : AB10, " & "qdr1_K_H_0 : AP19, " & "qdr1_K_H_1 : AR23, " & "PCI_GNT_L_0 : K1, " & "PCI_GNT_L_1 : L1, " & "FC_RXCSOF_L : AL2, " & "RDR0_CFM : C9, " & "VREFLO : (AC12, " & "AL6), " & "FC_RXCCLK_L : AM2, " & "qdr0_A_H_10 : AR18, " & "PCI_IRDY_L : P7, " & "qdr0_A_H_11 : AG18, " & "QDR3_Q_H_0 : T27, " & "qdr0_A_H_12 : AF18, " & "QDR3_Q_H_1 : R27, " & "qdr0_A_H_13 : AU17, " & "QDR3_Q_H_2 : R28, " & "qdr0_A_H_14 : AJ17, " & "QDR3_Q_H_3 : M30, " & "qdr0_A_H_15 : AU15, " & "QDR3_Q_H_4 : K35, " & "qdr0_A_H_16 : AT16, " & "QDR3_Q_H_5 : J35, " & "qdr0_A_H_17 : AN14, " & "QDR3_Q_H_6 : J32, " & "qdr0_A_H_18 : AN13, " & "FC_RXCSRB_L : AP2, " & "QDR3_Q_H_7 : K31, " & "qdr0_A_H_19 : AK18, " & "QDR3_Q_H_8 : L30, " & "QDR3_Q_H_9 : H32, " & "qdr0_C_L_0 : AR12, " & "qdr0_C_L_1 : AU9, " & "RDR1_SCK : D13, " & "PAR0_PADVREFA : F9, " & "qdr0_K_L_0 : AH19, " & "PAR0_PADVREFB : F6, " & "qdr0_K_L_1 : AT14, " & "FC_RXCSOF : AL1, " & "qdr2_BWS_L_0 : AD31, " & "qdr2_BWS_L_1 : AF33, " & "qdr0_A_H_20 : AL17, " & "qdr0_A_H_21 : AR15, " & "qdr0_A_H_22 : AK17, " & "qdr0_A_H_23 : AK16, " & "FC_RXCPAR_L : AK4, " & "SP_RD_L : H24, " & "QDR2_CIN_H_0 : AM33, " & "QDR2_CIN_H_1 : AN33, " & "QDR1_CIN_L_0 : AR28, " & "QDR1_CIN_L_1 : AR29, " & "qdr2_ZQ_0 : AG32, " & "qdr2_ZQ_1 : AF30, " & "FC_TXCDAT_0 : AE12, " & "FC_TXCDAT_1 : AF9, " & "FC_TXCFC : AJ3, " & "FC_TXCDAT_2 : AG10, " & "FC_TXCDAT_3 : AH9, " & "PCI_DEVSEL_L : N5, " & "qdr3_A_H_0 : U36, " & "QDR3_Q_H_10 : H33, " & "qdr3_A_H_1 : AB36, " & "qdr1_D_H_0 : AH23, " & "PAS2_VCCA : AE25, " & "QDR3_Q_H_11 : J33, " & "qdr3_A_H_2 : AB34, " & "qdr1_D_H_1 : AK23, " & "QDR3_Q_H_12 : K33, " & "qdr3_A_H_3 : V29, " & "qdr1_D_H_2 : AG23, " & "QDR3_Q_H_13 : J36, " & "qdr3_A_H_4 : AA33, " & "qdr1_D_H_3 : AM25, " & "QDR3_Q_H_14 : L32, " & "qdr3_A_H_5 : AA32, " & "qdr1_D_H_4 : AR27, " & "QDR3_Q_H_15 : M31, " & "qdr3_A_H_6 : W35, " & "qdr1_D_H_5 : AN26, " & "SPI4_TDAT_L_10 : V5, " & "QDR3_Q_H_16 : N30, " & "qdr3_A_H_7 : AA30, " & "qdr1_D_H_6 : AJ24, " & "SPI4_TDAT_L_11 : T2, " & "QDR3_Q_H_17 : P29, " & "qdr3_A_H_8 : W28, " & "qdr1_D_H_7 : AM27, " & "SPI4_TDAT_L_12 : Y10, " & "qdr3_A_H_9 : V31, " & "qdr1_D_H_8 : AK26, " & "SPI4_TDAT_L_13 : Y6, " & "qdr1_D_H_9 : AL26, " & "SPI4_TDAT_L_14 : W7, " & "SPI4_TDAT_L_15 : W3, " & "VCCA_SPI4 : AB13, " & "RDR0_SIO : D1, " & "RDR1_CFM : C22, " & "FC_RXCSRB : AP1, " & "VREFHI_CLK : H29, " & "SPI4_RCTL_L : AD5, " & "SPI4_TSCLK : P4, " & "qdr3_D_H_10 : L36, " & "qdr3_D_H_11 : M37, " & "qdr3_D_H_12 : P35, " & "qdr3_D_H_13 : R35, " & "qdr3_D_H_14 : R32, " & "RDR0_RQ_0 : A5, " & "qdr3_D_H_15 : R30, " & "RDR0_RQ_1 : E6, " & "qdr3_D_H_16 : T30, " & "RDR0_RQ_2 : C6, " & "qdr3_D_H_17 : U28, " & "RDR0_RQ_3 : A6, " & "RDR0_RQ_4 : E7, " & "qdr3_WPS_L_0 : W33, " & "RDR0_RQ_5 : C7, " & "qdr3_WPS_L_1 : Y33, " & "RDR0_RQ_6 : A7, " & "RDR0_RQ_7 : E8, " & "qdr2_C_H_0 : AH35, " & "qdr2_C_H_1 : AJ37, " & "RDR1_SCLKN : B13, " & "SPI4_TPAR : AB3, " & "qdr2_K_H_0 : AF36, " & "RDR2_SCK : C26, " & "qdr2_K_H_1 : AG37, " & "SPI4_RPROT_L : AB11, " & "SPI4_TDAT_10 : V4, " & "SPI4_TDAT_11 : T1, " & "SPI4_TDAT_12 : Y9, " & "SPI4_TDAT_13 : Y5, " & "SPI4_TDAT_14 : W6, " & "SPI4_TDAT_15 : W2, " & "TEST_SCAN_CLK_A : L28, " & "TEST_SCAN_CLK_B : M28, " & "CLK_CFG_RST_DIR : K23, " & "qdr3_RPS_L_0 : Y31, " & "qdr3_RPS_L_1 : W30, " & "FC_TXCFC_L : AJ4, " & "RDR0_CMD : B1, " & "FC_PREEMP : AG9, " & "qdr3_ZQ_0 : U30, " & "qdr3_ZQ_1 : U32, " & "qdr1_C_L_0 : AT26, " & "PCI_CLK : T9, " & "qdr1_C_L_1 : AU27, " & "qdr1_K_L_0 : AR19, " & "qdr1_K_L_1 : AT22, " & "qdr1_A_H_10 : AR24, " & "qdr1_A_H_11 : AL20, " & "qdr1_A_H_12 : AK20, " & "qdr1_A_H_13 : AR22, " & "qdr1_A_H_14 : AN24, " & "TEST_MODE_LOAD : M22, " & "RDR1_SIO : F14, " & "qdr1_A_H_15 : AR21, " & "qdr1_A_H_16 : AU21, " & "qdr1_A_H_17 : AH21, " & "qdr1_A_H_18 : AT20, " & "qdr1_A_H_19 : AN19, " & "RDR2_CFM : C34, " & "FC_TXCCLK : AH7, " & "PAS3_VCCA : R25, " & "SPI4_TDAT_0 : AA7, " & "SPI4_TDAT_1 : U4, " & "PCI_REQ_L_0 : U10, " & "SPI4_TDAT_2 : T5, " & "PCI_REQ_L_1 : N6, " & "SPI4_TDAT_3 : R1, " & "CLK_STOP : K22, " & "SPI4_TDAT_4 : Y7, " & "SPI4_TDAT_5 : V6, " & "qdr1_A_H_20 : AM19, " & "SPI4_TDAT_6 : V2, " & "qdr1_A_H_21 : AK21, " & "SPI4_TDAT_7 : V8, " & "qdr1_A_H_22 : AK19, " & "SPI4_TDAT_8 : Y3, " & "qdr1_A_H_23 : AF23, " & "SPI4_TDAT_9 : W11, " & "SPI4_PREEMP : T7, " & "VCCR : (G8, " & "G10, " & "G12, " & "G20, " & "G21, " & "G23, " & "G25, " & "G29, " & "G32, " & "G33, " & "G35, " & "G37, " & "G4, " & "G7), " & "qdr2_D_H_0 : AL33, " & "qdr2_D_H_1 : AP36, " & "qdr2_D_H_2 : AK31, " & "qdr2_D_H_3 : AK33, " & "qdr2_D_H_4 : AK35, " & "qdr2_D_H_5 : AJ30, " & "qdr2_D_H_6 : AE27, " & "qdr2_D_H_7 : AH30, " & "qdr2_D_H_8 : AE28, " & "qdr2_D_H_9 : AG30, " & "qdr3_BWS_L_0 : W32, " & "qdr3_BWS_L_1 : V33, " & "QDR3_CIN_H_0 : M33, " & "QDR3_CIN_H_1 : L33, " & "RDR1_RQ_0 : A17, " & "RDR1_RQ_1 : B18, " & "PCI_STOP_L : L15, " & "QDR2_CIN_L_0 : AM35, " & "RDR1_RQ_2 : D18, " & "QDR2_CIN_L_1 : AN35, " & "RDR1_RQ_3 : C19, " & "RDR1_RQ_4 : E19, " & "RDR1_RQ_5 : B20, " & "RDR1_RQ_6 : E21, " & "RDR1_RQ_7 : D20, " & "SPI4_RCLK_L : AC5, " & "SP_ACK_L : J25, " & "PAR1_PADVREFA : F20, " & "RDR0_DQA_0 : E10, " & "VCC33_PCI : (H1, " & "H13, " & "H16, " & "H7, " & "L14, " & "L3, " & "L8, " & "M17, " & "P11, " & "R4, " & "R5, " & "U8), " & "PAR1_PADVREFB : F18, " & "RDR0_DQA_1 : C10, " & "RDR0_DQA_2 : A10, " & "RDR0_DQA_3 : E11, " & "RDR0_DQA_4 : C11, " & "RDR0_DQA_5 : A11, " & "RDR0_DQA_6 : A12, " & "RDR0_DQA_7 : C12, " & "RDR0_DQA_8 : E12, " & "VCCA_FC : AC13, " & "FC_RXCDAT_L_0 : AP4, " & "FC_RXCDAT_L_1 : AN4, " & "FC_RXCDAT_L_2 : AM4, " & "FC_RXCDAT_L_3 : AK6, " & "PCI_IDSEL : M3, " & "RDR1_CMD : A13, " & "qdr3_C_H_0 : U35, " & "qdr3_C_H_1 : U33, " & "RDR2_SCLKN : D26, " & "qdr3_K_H_0 : W36, " & "SPI4_ZQ1 : AC9, " & "qdr3_K_H_1 : U37, " & "SPI4_ZQ2 : AC10, " & "PCI_PERR_L : T11, " & "SPI4_RPAR_L : AB9, " & "FC_TXCSOF : AJ5, " & "RDR2_SIO : A26, " & "SPI4_RCLK_REF : Y11, " & "PCI_PAR64 : K8, " & "RDR0_CTMN : A8, " & "VDDQ : (AA26, " & "AA31, " & "AB28, " & "AB33, " & "AB35, " & "AC31, " & "AC34, " & "AC36, " & "AD28, " & "AE31, " & "AE34, " & "AE36, " & "AF15, " & "AF26, " & "AF28, " & "AG31, " & "AG34, " & "AG36, " & "AH11, " & "AH13, " & "AH15, " & "AH17, " & "AH20, " & "AH22, " & "AH24, " & "AH26, " & "AH28, " & "AJ31, " & "AJ34, " & "AJ36, " & "AK8, " & "AL10, " & "AL12, " & "AL14, " & "AL16, " & "AL19, " & "AL21, " & "AL23, " & "AL25, " & "AL27, " & "AL29, " & "AL34, " & "AL36, " & "AN34, " & "AN36, " & "AP11, " & "AP13, " & "AP15, " & "AP17, " & "AP21, " & "AP23, " & "AP25, " & "AP27, " & "AP29, " & "AP31, " & "AP33, " & "AP5, " & "AP9, " & "AR2, " & "AR36, " & "AR4, " & "AT1, " & "AT11, " & "AT13, " & "AT15, " & "AT17, " & "AT19, " & "AT21, " & "AT23, " & "AT25, " & "AT27, " & "AT29, " & "AT31, " & "AT33, " & "AT35, " & "AT5, " & "AT7, " & "AT9, " & "H34, " & "H35, " & "J31, " & "K34, " & "K36, " & "L31, " & "M34, " & "M36, " & "N31, " & "P28, " & "P34, " & "P36, " & "R31, " & "T28, " & "T34, " & "T36, " & "U31, " & "V28, " & "V34, " & "W31, " & "Y28, " & "Y34, " & "Y36), " & "RDR0_DQB_0 : E5, " & "RDR0_DQB_1 : C5, " & "RDR0_DQB_2 : A4, " & "RDR0_DQB_3 : C4, " & "RDR0_DQB_4 : E4, " & "RDR0_DQB_5 : A3, " & "RDR0_DQB_6 : C3, " & "SPI4_RDAT_L_0 : AH1, " & "RDR0_DQB_7 : E3, " & "SPI4_RDAT_L_1 : AG3, " & "RDR0_DQB_8 : A2, " & "SPI4_RDAT_L_2 : AE3, " & "SPI4_RDAT_L_3 : AF5, " & "SPI4_RDAT_L_4 : AG1, " & "SPI4_RDAT_L_5 : AF1, " & "qdr0_WPS_L_0 : AN15, " & "SPI4_RDAT_L_6 : AE7, " & "qdr0_WPS_L_1 : AN18, " & "SPI4_RDAT_L_7 : AD1, " & "SPI4_RDAT_L_8 : AF7, " & "SPI4_RDAT_L_9 : AG5, " & "qdr2_C_L_0 : AJ35, " & "SP_WR_L : L26, " & "SP_AD_0 : H19, " & "qdr2_C_L_1 : AL37, " & "SP_AD_1 : H25, " & "SP_AD_2 : K27, " & "FC_RXCPAR : AK3, " & "SP_AD_3 : L27, " & "SP_AD_4 : K20, " & "SP_AD_5 : H28, " & "SP_AD_6 : J28, " & "qdr2_K_L_0 : AC37, " & "SP_AD_7 : J24, " & "qdr2_K_L_1 : AE37, " & "PCI_AD_10 : J3, " & "PCI_AD_11 : K13, " & "PCI_AD_12 : R11, " & "VCC_PLL : P25, " & "PCI_AD_13 : K4, " & "PCI_AD_14 : M14, " & "PCI_AD_15 : H2, " & "PCI_AD_16 : M7, " & "PCI_AD_17 : L4, " & "PCI_AD_18 : T10, " & "PCI_AD_19 : N7, " & "FC_TXCSOF_L : AJ6, " & "VCC_FUSE : (AD13, " & "AD14, " & "AE13, " & "AE14), " & "QDR0_Q_H_10 : AK10, " & "QDR0_Q_H_11 : AL8, " & "QDR0_Q_H_12 : AL9, " & "QDR0_Q_H_13 : AM8, " & "QDR0_Q_H_14 : AR7, " & "QDR0_Q_H_15 : AR6, " & "QDR0_Q_H_16 : AT4, " & "QDR0_Q_H_17 : AP7, " & "RDR0_CTM : A9, " & "FC_TXCCLK_L : AH8, " & "QDR0_Q_H_0 : AM6, " & "FC_TXCSRB : AF12, " & "QDR0_Q_H_1 : AN6, " & "QDR0_Q_H_2 : AT3, " & "PCI_CBE_L_0 : L13, " & "qdr2_A_H_10 : AC35, " & "QDR0_Q_H_3 : AR5, " & "PCI_CBE_L_1 : R10, " & "qdr2_A_H_11 : AB29, " & "SPI4_TCTL_L : AA4, " & "QDR0_Q_H_4 : AN7, " & "PCI_AD_20 : K3, " & "PCI_CBE_L_2 : T12, " & "qdr2_A_H_12 : AA28, " & "QDR0_Q_H_5 : AM7, " & "PCI_AD_21 : L6, " & "PCI_CBE_L_3 : N4, " & "qdr2_A_H_13 : AD36, " & "QDR0_Q_H_6 : AJ11, " & "PCI_AD_22 : M4, " & "PCI_CBE_L_4 : J15, " & "qdr2_A_H_14 : AB31, " & "FC_ZQ1 : AL7, " & "QDR0_Q_H_7 : AH12, " & "PCI_AD_23 : R9, " & "PCI_CBE_L_5 : N10, " & "qdr2_A_H_15 : AF35, " & "FC_ZQ2 : AK7, " & "qdr0_RPS_L_0 : AK15, " & "QDR0_Q_H_8 : AG14, " & "PCI_AD_24 : U12, " & "PCI_CBE_L_6 : M15, " & "qdr2_A_H_16 : AE35, " & "qdr0_RPS_L_1 : AL15, " & "QDR0_Q_H_9 : AH14, " & "PCI_AD_25 : K12, " & "PCI_CBE_L_7 : K7, " & "qdr2_A_H_17 : AH36, " & "JTAG_TCK : M20, " & "PCI_AD_26 : P6, " & "qdr2_A_H_18 : AB27, " & "PCI_AD_27 : U11, " & "qdr2_A_H_19 : AA27, " & "FC_TXCSRB_L : AF11, " & "PCI_AD_28 : L2, " & "PCI_AD_29 : J1, " & "RDR2_RQ_0 : A30, " & "RDR2_RQ_1 : A31, " & "RDR2_RQ_2 : C31, " & "RDR2_CMD : E26, " & "RDR2_RQ_3 : E31, " & "RDR2_RQ_4 : A32, " & "RDR2_RQ_5 : C32, " & "RDR2_RQ_6 : E32, " & "RDR2_RQ_7 : E33, " & "qdr3_D_H_0 : U27, " & "qdr3_D_H_1 : T29, " & "qdr3_D_H_2 : U26, " & "qdr3_D_H_3 : P31, " & "qdr3_D_H_4 : R33, " & "qdr3_D_H_5 : P33, " & "qdr3_D_H_6 : P30, " & "qdr3_D_H_7 : N33, " & "qdr3_D_H_8 : N32, " & "RDR0_CFMN : C8, " & "qdr3_D_H_9 : K37, " & "qdr2_A_H_20 : AC33, " & "qdr0_D_H_10 : AJ13, " & "qdr2_A_H_21 : AC30, " & "qdr0_D_H_11 : AL13, " & "PCI_AD_30 : M6, " & "qdr2_A_H_22 : AC32, " & "qdr0_D_H_12 : AK12, " & "PCI_AD_31 : M5, " & "qdr2_A_H_23 : AE30, " & "qdr0_D_H_13 : AR11, " & "PCI_AD_32 : K11, " & "FC_TXCPAR_L : AJ8, " & "qdr0_D_H_14 : AN11, " & "PCI_AD_33 : H9, " & "JTAG_TDI : J23, " & "qdr0_D_H_15 : AN10, " & "PCI_AD_34 : J11, " & "qdr0_D_H_16 : AT6, " & "PCI_AD_35 : H8, " & "qdr0_D_H_17 : AM10, " & "PCI_AD_36 : K18, " & "PCI_AD_37 : M12, " & "PCI_AD_38 : H6, " & "SPI4_RCLK : AC6, " & "PCI_AD_39 : J16, " & "JTAG_TDO : M25, " & "PCI_INTA_L : M2, " & "SPI4_TCLK_REF_L : AD7, " & "TEST_CLK : M21, " & "RDR1_DQA_0 : A23, " & "RDR1_DQA_1 : C23, " & "RDR1_DQA_2 : A24, " & "RDR1_DQA_3 : E23, " & "RDR1_DQA_4 : C24, " & "SP_DIR : K28, " & "RDR1_DQA_5 : E24, " & "RDR1_DQA_6 : A25, " & "PCI_AD_40 : J10, " & "RDR1_DQA_7 : E25, " & "PCI_AD_41 : J18, " & "RDR1_DQA_8 : C25, " & "PCI_AD_42 : H5, " & "PCI_AD_43 : L17, " & "VREFLO_CLK : H30, " & "PCI_AD_44 : J9, " & "PCI_AD_45 : K10, " & "PCI_AD_46 : M11, " & "RDR1_CTMN : A21, " & "PCI_AD_47 : H15, " & "CLK_PLL_BYP : P26, " & "PCI_AD_48 : J8, " & "PCI_AD_49 : K16, " & "qdr0_A_H_0 : AL18, " & "qdr0_A_H_1 : AT8, " & "qdr0_A_H_2 : AT10, " & "qdr0_A_H_3 : AG19, " & "qdr0_A_H_4 : AU13, " & "qdr0_A_H_5 : AT12, " & "qdr0_A_H_6 : AR16, " & "qdr0_A_H_7 : AM18, " & "qdr0_A_H_8 : AN17, " & "qdr0_A_H_9 : AH18, " & "SPI4_RSTAT_0 : N1, " & "qdr0_BWS_L_0 : AR14, " & "SP_CLK : M26, " & "SPI4_RSTAT_1 : N3, " & "qdr0_BWS_L_1 : AN16, " & "SPI4_TPROT_L : AA2, " & "PCI_AD_50 : L18, " & "PCI_AD_51 : K14, " & "QDR0_CIN_H_0 : AN9, " & "PCI_AD_52 : N12, " & "QDR0_CIN_H_1 : AN8, " & "PCI_AD_53 : H11, " & "PCI_AD_54 : K9, " & "PCI_AD_55 : J7, " & "PCI_AD_56 : J6, " & "PCI_AD_57 : K15, " & "PCI_AD_58 : N11, " & "QDR3_CIN_L_0 : N35, " & "PCI_AD_59 : H12, " & "QDR3_CIN_L_1 : M35, " & "PCI_INTB_L : R7, " & "RDR1_CTM : A22, " & "RDR1_DQB_0 : E17, " & "RDR1_DQB_1 : C17, " & "RDR1_DQB_2 : C16, " & "RDR1_DQB_3 : E16, " & "RDR1_DQB_4 : A16, " & "RDR1_DQB_5 : C15, " & "RDR1_DQB_6 : E15, " & "RDR1_DQB_7 : A15, " & "PCI_AD_60 : L10, " & "VCCRIO : (G15, " & "G1, " & "G11, " & "G17, " & "G24, " & "G26, " & "G28, " & "G3, " & "G36), " & "RDR1_DQB_8 : A14, " & "PCI_AD_61 : J5, " & "PCI_AD_62 : M10, " & "PCI_AD_63 : L16, " & "RDR0_PCLKM : D2, " & "SPI4_RDAT_L_10 : AF3, " & "VCC_CLK : J19, " & "qdr3_C_L_0 : T35, " & "SPI4_RDAT_L_11 : AB5, " & "qdr3_C_L_1 : T33, " & "SPI4_RDAT_L_12 : AD9, " & "SPI4_RDAT_L_13 : AB7, " & "SPI4_RDAT_L_14 : AD3, " & "SPI4_RDAT_L_15 : AC1, " & "PAR2_PADVREFA : F34, " & "qdr3_K_L_0 : AA37, " & "PAR2_PADVREFB : F31, " & "qdr3_K_L_1 : AA36, " & "PCI_ACK64_L : J14, " & "SR_RX : H22, " & "CLK_RST_DIS : N26, " & "SPI4_TCLK_L : T4, " & "RDR1_CFMN : C21, " & "FC_RXCDAT_0 : AP3, " & "QDR1_Q_H_0 : AF24, " & "FC_RXCDAT_1 : AN3, " & "QDR1_Q_H_1 : AG25, " & "FC_RXCDAT_2 : AM3, " & "VSS : (A37, " & "AA12, " & "AA14, " & "AA16, " & "AA18, " & "AA20, " & "AA22, " & "AA24, " & "AA29, " & "AA34, " & "AA5, " & "AA9, " & "AB1, " & "AB15, " & "AB17, " & "AB19, " & "AB21, " & "AB23, " & "AB25, " & "AB26, " & "AB32, " & "AB37, " & "AC14, " & "AC16, " & "AC18, " & "AC20, " & "AC22, " & "AC24, " & "AC26, " & "AC27, " & "AC29, " & "AC3, " & "AC7, " & "AD12, " & "AD15, " & "AD17, " & "AD19, " & "AD21, " & "AD23, " & "AD25, " & "AD26, " & "AD27, " & "AD32, " & "AD34, " & "AD37, " & "AE1, " & "AE16, " & "AE18, " & "AE20, " & "AE22, " & "AE26, " & "AE29, " & "AE5, " & "AE9, " & "AF13, " & "AF14, " & "AF16, " & "AF17, " & "AF20, " & "AF25, " & "AF32, " & "AF34, " & "AF37, " & "AG12, " & "AG13, " & "AG17, " & "AG22, " & "AG29, " & "AG7, " & "AH10, " & "AH16, " & "AH3, " & "AH32, " & "AH34, " & "AH37, " & "AH5, " & "AJ1, " & "AJ10, " & "AJ12, " & "AJ14, " & "AJ15, " & "AJ16, " & "AJ18, " & "AJ19, " & "AJ21, " & "AJ23, " & "AJ25, " & "AJ27, " & "AJ29, " & "AK32, " & "AK34, " & "AK37, " & "AK9, " & "AL3, " & "AM11, " & "AM13, " & "AM15, " & "AM16, " & "AM17, " & "AM20, " & "AM22, " & "AM24, " & "AM26, " & "AM28, " & "AM30, " & "AM32, " & "AM34, " & "AM37, " & "AM5, " & "AM9, " & "AN2, " & "AP10, " & "AP12, " & "AP14, " & "AP16, " & "AP18, " & "AP20, " & "AP22, " & "AP24, " & "AP26, " & "AP28, " & "AP30, " & "AP32, " & "AP34, " & "AP37, " & "AP6, " & "AP8, " & "AR1, " & "AR3, " & "AU1, " & "AU10, " & "AU12, " & "AU14, " & "AU16, " & "AU2, " & "AU22, " & "AU24, " & "AU26, " & "AU28, " & "AU30, " & "AU32, " & "AU34, " & "AU37, " & "AU4, " & "AU6, " & "AU8, " & "B10, " & "B11, " & "B12, " & "B14, " & "B15, " & "B16, " & "B17, " & "B19, " & "B2, " & "B21, " & "B22, " & "B23, " & "B24, " & "B25, " & "B26, " & "B27, " & "B28, " & "B29, " & "B3, " & "B30, " & "B31, " & "B32, " & "B33, " & "B34, " & "B35, " & "B36, " & "B4, " & "B5, " & "B6, " & "B7, " & "B8, " & "B9, " & "C1, " & "C13, " & "C14, " & "C18, " & "C2, " & "C20, " & "C27, " & "C37, " & "D10, " & "D11, " & "D12, " & "D15, " & "D16, " & "D17, " & "D19, " & "D21, " & "D22, " & "D23, " & "D24, " & "D25, " & "D28, " & "D29, " & "D3, " & "D30, " & "D31, " & "D32, " & "D33, " & "D34, " & "D35, " & "D36, " & "D4, " & "D5, " & "D6, " & "D7, " & "D8, " & "D9, " & "E1, " & "E13, " & "E14, " & "E18, " & "E2, " & "E20, " & "E22, " & "E27, " & "E34, " & "E37, " & "E9, " & "F10, " & "F11, " & "F12, " & "F13, " & "F15, " & "F16, " & "F17, " & "F19, " & "F21, " & "F22, " & "F23, " & "F24, " & "F25, " & "F26, " & "F27, " & "F28, " & "F29, " & "F3, " & "F30, " & "F32, " & "F33, " & "F35, " & "F36, " & "F4, " & "F5, " & "F7, " & "F8, " & "G13, " & "G14, " & "G16, " & "G18, " & "G2, " & "G27, " & "G31, " & "G6, " & "H10, " & "H14, " & "H17, " & "H18, " & "H23, " & "H31, " & "H4, " & "J30, " & "J34, " & "J37, " & "K17, " & "K19, " & "K2, " & "K30, " & "K32, " & "L11, " & "L19, " & "L23, " & "L34, " & "L35, " & "L37, " & "L5, " & "M1, " & "M16, " & "M19, " & "M32, " & "N14, " & "N16, " & "N18, " & "N20, " & "N22, " & "N24, " & "N29, " & "N34, " & "N37, " & "P13, " & "P15, " & "P17, " & "P19, " & "P2, " & "P21, " & "P23, " & "P27, " & "P32, " & "P9, " & "R14, " & "R16, " & "R18, " & "R20, " & "R22, " & "R24, " & "R29, " & "R3, " & "R34, " & "R37, " & "R6, " & "T13, " & "T15, " & "T17, " & "T19, " & "T21, " & "T23, " & "T25, " & "T26, " & "T32, " & "U14, " & "U16, " & "U18, " & "U2, " & "U20, " & "U22, " & "U24, " & "U29, " & "U34, " & "U6, " & "U9, " & "V10, " & "V12, " & "V13, " & "V15, " & "V17, " & "V19, " & "V21, " & "V23, " & "V25, " & "V26, " & "V32, " & "V36, " & "W10, " & "W14, " & "W16, " & "W18, " & "W20, " & "W22, " & "W24, " & "W26, " & "W29, " & "W34, " & "W4, " & "W8, " & "Y13, " & "Y15, " & "Y17, " & "Y19, " & "Y2, " & "Y21, " & "Y23, " & "Y25, " & "Y26, " & "Y32), " & "VCC : (AA13, " & "AA15, " & "AA17, " & "AA19, " & "AA21, " & "AA23, " & "AA25, " & "AB14, " & "AB16, " & "AB18, " & "AB20, " & "AB22, " & "AB24, " & "AC15, " & "AC17, " & "AC19, " & "AC21, " & "AC23, " & "AC25, " & "AD16, " & "AD18, " & "AD20, " & "AD22, " & "AD24, " & "AE17, " & "AE19, " & "AE21, " & "AE23, " & "N13, " & "N15, " & "N17, " & "N19, " & "N21, " & "N23, " & "P14, " & "P16, " & "P18, " & "P20, " & "P22, " & "P24, " & "R13, " & "R15, " & "R17, " & "R19, " & "R21, " & "R23, " & "T14, " & "T16, " & "T18, " & "T20, " & "T22, " & "T24, " & "U13, " & "U15, " & "U17, " & "U19, " & "U21, " & "U23, " & "U25, " & "V14, " & "V16, " & "V18, " & "V20, " & "V22, " & "V24, " & "W13, " & "W15, " & "W17, " & "W19, " & "W21, " & "W23, " & "W25, " & "Y14, " & "Y16, " & "Y18, " & "Y20, " & "Y22, " & "Y24) "; attribute PORT_GROUPING of IXP2800_B1 : entity is "Differential_Voltage ( " & "(FC_TXCDAT_1 , FC_TXCDAT_L_1 ) , " & "(FC_TXCFC , FC_TXCFC_L ) , " & "(FC_RXCDAT_3 , FC_RXCDAT_L_3 ) , " & "(SPI4_TDAT_5 , SPI4_TDAT_L_5 ) , " & "(SPI4_RDAT_7 , SPI4_RDAT_L_7 ) , " & "(FC_TXCDAT_2 , FC_TXCDAT_L_2 ) , " & "(SPI4_TDAT_6 , SPI4_TDAT_L_6 ) , " & "(SPI4_RDAT_8 , SPI4_RDAT_L_8 ) , " & "(FC_TXCDAT_3 , FC_TXCDAT_L_3 ) , " & "(SPI4_TDAT_7 , SPI4_TDAT_L_7 ) , " & "(SPI4_RDAT_9 , SPI4_RDAT_L_9 ) , " & "(SPI4_TDAT_8 , SPI4_TDAT_L_8 ) , " & "(SPI4_TDAT_9 , SPI4_TDAT_L_9 ) , " & "(SPI4_RPAR , SPI4_RPAR_L ) , " & "(SPI4_RPROT , SPI4_RPROT_L ) , " & "(SPI4_TPAR , SPI4_TPAR_L ) , " & "(FC_RXCPAR , FC_RXCPAR_L ) , " & "(SPI4_TPROT , SPI4_TPROT_L ) , " & "(FC_TXCPAR , FC_TXCPAR_L ) , " & "(FC_RXCSOF , FC_RXCSOF_L ) , " & "(FC_TXCSOF , FC_TXCSOF_L ) , " & "(SPI4_RCLK_REF , SPI4_RCLK_REF_L ) , " & "(SPI4_TCLK_REF , SPI4_TCLK_REF_L ) , " & "(SPI4_RDAT_10 , SPI4_RDAT_L_10 ) , " & "(SPI4_RDAT_11 , SPI4_RDAT_L_11 ) , " & "(SPI4_RCLK , SPI4_RCLK_L ) , " & "(SPI4_RDAT_12 , SPI4_RDAT_L_12 ) , " & "(SPI4_TDAT_10 , SPI4_TDAT_L_10 ) , " & "(SPI4_RDAT_13 , SPI4_RDAT_L_13 ) , " & "(SPI4_TCLK , SPI4_TCLK_L ) , " & "(SPI4_TDAT_11 , SPI4_TDAT_L_11 ) , " & "(SPI4_RDAT_14 , SPI4_RDAT_L_14 ) , " & "(SPI4_TDAT_12 , SPI4_TDAT_L_12 ) , " & "(FC_RXCCLK , FC_RXCCLK_L ) , " & "(SPI4_RDAT_15 , SPI4_RDAT_L_15 ) , " & "(SPI4_TDAT_13 , SPI4_TDAT_L_13 ) , " & "(SPI4_TDAT_14 , SPI4_TDAT_L_14 ) , " & "(FC_TXCCLK , FC_TXCCLK_L ) , " & "(SPI4_TDAT_15 , SPI4_TDAT_L_15 ) , " & "(SPI4_RCTL , SPI4_RCTL_L ) , " & "(SPI4_TCTL , SPI4_TCTL_L ) , " & "(SPI4_RDAT_0 , SPI4_RDAT_L_0 ) , " & "(SPI4_RDAT_1 , SPI4_RDAT_L_1 ) , " & "(SPI4_TDAT_0 , SPI4_TDAT_L_0 ) , " & "(SPI4_RDAT_2 , SPI4_RDAT_L_2 ) , " & "(FC_RXCSRB , FC_RXCSRB_L ) , " & "(SPI4_TDAT_1 , SPI4_TDAT_L_1 ) , " & "(SPI4_RDAT_3 , SPI4_RDAT_L_3 ) , " & "(FC_RXCDAT_0 , FC_RXCDAT_L_0 ) , " & "(SPI4_TDAT_2 , SPI4_TDAT_L_2 ) , " & "(SPI4_RDAT_4 , SPI4_RDAT_L_4 ) , " & "(FC_TXCSRB , FC_TXCSRB_L ) , " & "(FC_RXCFC , FC_RXCFC_L ) , " & "(FC_RXCDAT_1 , FC_RXCDAT_L_1 ) , " & "(SPI4_TDAT_3 , SPI4_TDAT_L_3 ) , " & "(SPI4_RDAT_5 , SPI4_RDAT_L_5 ) , " & "(FC_TXCDAT_0 , FC_TXCDAT_L_0 ) , " & "(FC_RXCDAT_2 , FC_RXCDAT_L_2 ) , " & "(SPI4_TDAT_4 , SPI4_TDAT_L_4 ) , " & "(SPI4_RDAT_6 , SPI4_RDAT_L_6 ) ) "; attribute TAP_SCAN_OUT of JTAG_TDO : signal is true; attribute TAP_SCAN_RESET of JTAG_TRST : signal is true; attribute TAP_SCAN_CLOCK of JTAG_TCK : signal is (1.0e6,BOTH); attribute TAP_SCAN_MODE of JTAG_TMS : signal is true; attribute TAP_SCAN_IN of JTAG_TDI : signal is true; attribute COMPLIANCE_PATTERNS of IXP2800_B1 : entity is "(TEST_CLK ," & "TEST_MODE_LOAD," & "TEST_SCAN_EN," & "TEST_SCAN_CLK_A," & "TEST_SCAN_CLK_B," & "CLK_NRESET," & "CLK_CFG_RST_DIR," & "CLK_STOP," & "CLK_PLL_BYP," & "CLK_RST_DIS)" & "(0001100000)"; attribute INSTRUCTION_LENGTH of IXP2800_B1 : entity is 7; attribute INSTRUCTION_OPCODE of IXP2800_B1 : entity is "SAMPLE (0100001), " & "IDCODE (1111110), " & "CLAMP (0100010), " & "BYPASS (1111111), " & "HIGHZ (0100011), " & "EXTEST (0000000), " & "ILLEGAL_1 (0101110), " & "ILLEGAL_2 (0101101), " & "ILLEGAL_3 (0001100), " & "ILLEGAL_4 (0101111), " & "ILLEGAL_5 (0001001), " & "ILLEGAL_6 (0100000), " & "ILLEGAL_7 (0000011), " & "ILLEGAL_8 (0100100), " & "ILLEGAL_9 (0101001), " & "ILLEGAL_A (0100101), " & "ILLEGAL_B (0001010), " & "ILLEGAL_C (0000010), " & "ILLEGAL_D (0100110), " & "ILLEGAL_E (0100111), " & "ILLEGAL_F (0010000), " & "ILLEGAL_G (0000111), " & "ILLEGAL_H (0101000), " & "ILLEGAL_I (0101100), " & "ILLEGAL_J (0101010), " & "ILLEGAL_K (0101011)"; attribute INSTRUCTION_CAPTURE of IXP2800_B1 : entity is "xxxxx01"; attribute INSTRUCTION_PRIVATE of IXP2800_B1 : entity is "ILLEGAL_1 , " & "ILLEGAL_2 , " & "ILLEGAL_3 , " & "ILLEGAL_4 , " & "ILLEGAL_5 , " & "ILLEGAL_6 , " & "ILLEGAL_7 , " & "ILLEGAL_8 , " & "ILLEGAL_9 , " & "ILLEGAL_A , " & "ILLEGAL_B , " & "ILLEGAL_C , " & "ILLEGAL_D , " & "ILLEGAL_E , " & "ILLEGAL_F , " & "ILLEGAL_G , " & "ILLEGAL_H , " & "ILLEGAL_I , " & "ILLEGAL_J , " & "ILLEGAL_K "; attribute IDCODE_REGISTER of IXP2800_B1 : entity is "0101" & --Version "1001001001110011" & --Part number "00000001001" & --Identity of manufacturer "1"; -- Required by IEEE Std 1149.1-1990 attribute BOUNDARY_LENGTH of IXP2800_B1 : entity is 1208; attribute BOUNDARY_REGISTER of IXP2800_B1 : entity is " 0 (BC_1, * , control , 0)," & " 1 (BC_1, QDR0_A_H_13 , output3 , X, 0, 0, Z)," & " 2 (BC_1, * , control , 0)," & " 3 (BC_1, QDR0_A_H_7 , output3 , X, 2, 0, Z)," & " 4 (BC_1, * , control , 0)," & " 5 (BC_1, QDR0_A_H_15 , output3 , X, 4, 0, Z)," & " 6 (BC_1, * , control , 0)," & " 7 (BC_1, QDR0_A_H_0 , output3 , X, 6, 0, Z)," & " 8 (BC_1, * , control , 0)," & " 9 (BC_1, QDR0_K_H_0 , output3 , X, 8, 0, Z)," & " 10 (BC_1, * , control , 0)," & " 11 (BC_1, QDR0_K_L_0 , output3 , X, 10, 0, Z)," & " 12 (BC_1, * , control , 0)," & " 13 (BC_1, QDR0_A_H_3 , output3 , X, 12, 0, Z)," & " 14 (BC_1, * , control , 0)," & " 15 (BC_1, QDR0_A_H_16 , output3 , X, 14, 0, Z)," & " 16 (BC_1, * , control , 0)," & " 17 (BC_1, QDR0_K_L_1 , output3 , X, 16, 0, Z)," & " 18 (BC_1, * , control , 0)," & " 19 (BC_1, QDR0_K_H_1 , output3 , X, 18, 0, Z)," & " 20 (BC_1, * , internal , 0)," & " 21 (BC_1, * , internal , 0)," & " 22 (BC_1, * , control , 0)," & " 23 (BC_1, QDR0_A_H_21 , output3 , X, 22, 0, Z)," & " 24 (BC_1, * , control , 0)," & " 25 (BC_1, QDR0_A_H_4 , output3 , X, 24, 0, Z)," & " 26 (BC_1, * , control , 0)," & " 27 (BC_1, QDR0_A_H_6 , output3 , X, 26, 0, Z)," & " 28 (BC_1, * , control , 0)," & " 29 (BC_1, QDR0_A_H_10 , output3 , X, 28, 0, Z)," & " 30 (BC_1, * , control , 0)," & " 31 (BC_1, QDR0_A_H_5 , output3 , X, 30, 0, Z)," & " 32 (BC_1, * , control , 0)," & " 33 (BC_1, QDR0_A_H_19 , output3 , X, 32, 0, Z)," & " 34 (BC_1, * , control , 0)," & " 35 (BC_1, QDR0_A_H_22 , output3 , X, 34, 0, Z)," & " 36 (BC_1, * , control , 0)," & " 37 (BC_1, QDR0_BWS_L_0 , output3 , X, 36, 0, Z)," & " 38 (BC_1, * , internal , 0)," & " 39 (BC_1, * , internal , 0)," & " 40 (BC_1, * , control , 0)," & " 41 (BC_1, QDR0_A_H_20 , output3 , X, 40, 0, Z)," & " 42 (BC_1, * , control , 0)," & " 43 (BC_1, QDR0_A_H_9 , output3 , X, 42, 0, Z)," & " 44 (BC_1, * , control , 0)," & " 45 (BC_1, QDR0_A_H_11 , output3 , X, 44, 0, Z)," & " 46 (BC_1, * , control , 0)," & " 47 (BC_1, QDR0_A_H_12 , output3 , X, 46, 0, Z)," & " 48 (BC_1, * , control , 0)," & " 49 (BC_1, QDR0_A_H_23 , output3 , X, 48, 0, Z)," & " 50 (BC_1, * , control , 0)," & " 51 (BC_1, QDR0_A_H_14 , output3 , X, 50, 0, Z)," & " 52 (BC_1, * , control , 0)," & " 53 (BC_1, QDR0_A_H_8 , output3 , X, 52, 0, Z)," & " 54 (BC_1, * , control , 0)," & " 55 (BC_1, QDR0_WPS_L_1 , output3 , X, 54, 0, Z)," & " 56 (BC_1, * , control , 0)," & " 57 (BC_1, QDR0_RPS_L_1 , output3 , X, 56, 0, Z)," & " 58 (BC_1, * , control , 0)," & " 59 (BC_1, QDR0_RPS_L_0 , output3 , X, 58, 0, Z)," & " 60 (BC_1, * , control , 0)," & " 61 (BC_1, QDR0_BWS_L_1 , output3 , X, 60, 0, Z)," & " 62 (BC_1, * , control , 0)," & " 63 (BC_1, QDR0_WPS_L_0 , output3 , X, 62, 0, Z)," & " 64 (BC_1, * , control , 0)," & " 65 (BC_1, QDR0_C_H_1 , output3 , X, 64, 0, Z)," & " 66 (BC_1, * , control , 0)," & " 67 (BC_1, QDR0_C_L_1 , output3 , X, 66, 0, Z)," & " 68 (BC_1, * , control , 0)," & " 69 (BC_1, QDR0_C_H_0 , output3 , X, 68, 0, Z)," & " 70 (BC_1, * , control , 0)," & " 71 (BC_1, QDR0_C_L_0 , output3 , X, 70, 0, Z)," & " 72 (BC_1, * , control , 0)," & " 73 (BC_1, QDR0_A_H_17 , output3 , X, 72, 0, Z)," & " 74 (BC_1, * , control , 0)," & " 75 (BC_1, QDR0_A_H_2 , output3 , X, 74, 0, Z)," & " 76 (BC_1, * , control , 0)," & " 77 (BC_1, QDR0_A_H_18 , output3 , X, 76, 0, Z)," & " 78 (BC_1, * , control , 0)," & " 79 (BC_1, QDR0_A_H_1 , output3 , X, 78, 0, Z)," & " 80 (BC_1, * , control , 0)," & " 81 (BC_1, QDR0_D_H_7 , output3 , X, 80, 0, Z)," & " 82 (BC_1, * , control , 0)," & " 83 (BC_1, QDR0_D_H_3 , output3 , X, 82, 0, Z)," & " 84 (BC_1, * , control , 0)," & " 85 (BC_1, QDR0_D_H_14 , output3 , X, 84, 0, Z)," & " 86 (BC_1, * , internal , 0)," & " 87 (BC_1, * , internal , 0)," & " 88 (BC_1, * , control , 0)," & " 89 (BC_1, QDR0_D_H_9 , output3 , X, 88, 0, Z)," & " 90 (BC_1, * , control , 0)," & " 91 (BC_1, QDR0_D_H_12 , output3 , X, 90, 0, Z)," & " 92 (BC_1, * , control , 0)," & " 93 (BC_1, QDR0_D_H_11 , output3 , X, 92, 0, Z)," & " 94 (BC_1, * , control , 0)," & " 95 (BC_1, QDR0_D_H_13 , output3 , X, 94, 0, Z)," & " 96 (BC_1, * , control , 0)," & " 97 (BC_1, QDR0_D_H_0 , output3 , X, 96, 0, Z)," & " 98 (BC_1, * , control , 0)," & " 99 (BC_1, QDR0_D_H_5 , output3 , X, 98, 0, Z)," & " 100 (BC_1, * , control , 0)," & " 101 (BC_1, QDR0_D_H_15 , output3 , X, 100, 0, Z)," & " 102 (BC_1, * , control , 0)," & " 103 (BC_1, QDR0_D_H_1 , output3 , X, 102, 0, Z)," & " 104 (BC_1, * , control , 0)," & " 105 (BC_1, QDR0_D_H_6 , output3 , X, 104, 0, Z)," & " 106 (BC_1, * , control , 0)," & " 107 (BC_1, QDR0_D_H_17 , output3 , X, 106, 0, Z)," & " 108 (BC_1, * , control , 0)," & " 109 (BC_1, QDR0_D_H_4 , output3 , X, 108, 0, Z)," & " 110 (BC_1, * , internal , 0)," & " 111 (BC_1, * , internal , 0)," & " 112 (BC_1, * , control , 0)," & " 113 (BC_1, QDR0_D_H_2 , output3 , X, 112, 0, Z)," & " 114 (BC_1, * , control , 0)," & " 115 (BC_1, QDR0_D_H_16 , output3 , X, 114, 0, Z)," & " 116 (BC_1, * , control , 0)," & " 117 (BC_1, QDR0_D_H_10 , output3 , X, 116, 0, Z)," & " 118 (BC_1, * , control , 0)," & " 119 (BC_1, QDR0_D_H_8 , output3 , X, 118, 0, Z)," & " 120 (BC_1, * , control , 0)," & " 121 (BC_7,QDR0_Q_H_14,bidir,X,120,0,Z)," & " 122 (BC_1, * , control , 0)," & " 123 (BC_7,QDR0_Q_H_13,bidir,X,122,0,Z)," & " 124 (BC_1, * , control , 0)," & " 125 (BC_7,QDR0_Q_H_16,bidir,X,124,0,Z)," & " 126 (BC_1, * , control , 0)," & " 127 (BC_7,QDR0_Q_H_12,bidir,X,126,0,Z)," & " 128 (BC_1, * , control , 0)," & " 129 (BC_7,QDR0_Q_H_3,bidir,X,128,0,Z)," & " 130 (BC_1, * , control , 0)," & " 131 (BC_7,QDR0_Q_H_17,bidir,X,130,0,Z)," & " 132 (BC_1, * , control , 0)," & " 133 (BC_7,QDR0_Q_H_10,bidir,X,132,0,Z)," & " 134 (BC_1, * , control , 0)," & " 135 (BC_7,QDR0_Q_H_9,bidir,X,134,0,Z)," & " 136 (BC_1, * , control , 0)," & " 137 (BC_7,QDR0_Q_H_6,bidir,X,136,0,Z)," & " 138 (BC_1, * , control , 0)," & " 139 (BC_7,QDR0_CIN_H_0,bidir,X,138,0,Z)," & " 140 (BC_1, * , control , 0)," & " 141 (BC_7,QDR0_CIN_L_0,bidir,X,140,0,Z)," & " 142 (BC_1, * , control , 0)," & " 143 (BC_7,QDR0_CIN_L_1,bidir,X,142,0,Z)," & " 144 (BC_1, * , control , 0)," & " 145 (BC_7,QDR0_CIN_H_1,bidir,X,144,0,Z)," & " 146 (BC_1, * , control , 0)," & " 147 (BC_7,QDR0_Q_H_2,bidir,X,146,0,Z)," & " 148 (BC_1, * , control , 0)," & " 149 (BC_7,QDR0_Q_H_4,bidir,X,148,0,Z)," & " 150 (BC_1, * , control , 0)," & " 151 (BC_7,QDR0_Q_H_15,bidir,X,150,0,Z)," & " 152 (BC_1, * , control , 0)," & " 153 (BC_7,QDR0_Q_H_0,bidir,X,152,0,Z)," & " 154 (BC_1, * , control , 0)," & " 155 (BC_7,QDR0_Q_H_11,bidir,X,154,0,Z)," & " 156 (BC_1, * , control , 0)," & " 157 (BC_7,QDR0_Q_H_7,bidir,X,156,0,Z)," & " 158 (BC_1, * , control , 0)," & " 159 (BC_7,QDR0_Q_H_5,bidir,X,158,0,Z)," & " 160 (BC_1, * , control , 0)," & " 161 (BC_7,QDR0_Q_H_8,bidir,X,160,0,Z)," & " 162 (BC_1, * , control , 0)," & " 163 (BC_7,QDR0_Q_H_1,bidir,X,162,0,Z)," & " 164 (BC_1, * , internal , 0)," & " 165 (BC_4, FC_RXCDAT_2 , input , X)," & " 166 (BC_1, * , internal , 0)," & " 167 (BC_4, FC_RXCDAT_1 , input , X)," & " 168 (BC_1, * , internal , 0)," & " 169 (BC_4, FC_RXCDAT_3 , input , X)," & " 170 (BC_1, * , internal , 0)," & " 171 (BC_4, FC_RXCDAT_0 , input , X)," & " 172 (BC_1, * , internal , 0)," & " 173 (BC_4, FC_RXCCLK , input , X)," & " 174 (BC_1, * , internal , 0)," & " 175 (BC_4, FC_RXCSRB , input , X)," & " 176 (BC_1, * , internal , 0)," & " 177 (BC_4, FC_RXCPAR , input , X)," & " 178 (BC_1, * , internal , 0)," & " 179 (BC_4, FC_RXCSOF , input , X)," & " 180 (BC_1, * , control , 0)," & " 181 (BC_1, FC_RXCFC , output3 , X, 180, 0, Z)," & " 182 (BC_1, * , control , 0)," & " 183 (BC_1, FC_TXCSRB , output3 , X, 182, 0, Z)," & " 184 (BC_1, * , control , 0)," & " 185 (BC_1, FC_TXCDAT_1 , output3 , X, 184, 0, Z)," & " 186 (BC_1, * , control , 0)," & " 187 (BC_1, FC_TXCDAT_2 , output3 , X, 186, 0, Z)," & " 188 (BC_1, * , control , 0)," & " 189 (BC_1, FC_TXCDAT_0 , output3 , X, 188, 0, Z)," & " 190 (BC_1, * , control , 0)," & " 191 (BC_1, FC_TXCDAT_3 , output3 , X, 190, 0, Z)," & " 192 (BC_1, * , control , 0)," & " 193 (BC_1, FC_TXCCLK , output3 , X, 192, 0, Z)," & " 194 (BC_1, * , control , 0)," & " 195 (BC_1, FC_TXCSOF , output3 , X, 194, 0, Z)," & " 196 (BC_1, * , control , 0)," & " 197 (BC_1, FC_TXCPAR , output3 , X, 196, 0, Z)," & " 198 (BC_1, * , internal , 0)," & " 199 (BC_4, FC_TXCFC , input , X)," & " 200 (BC_1, * , control , 0)," & " 201 (BC_7,FC_PREEMP,bidir,X,200,0,Z)," & " 202 (BC_1, * , internal , 0)," & " 203 (BC_4, SPI4_RDAT_8 , input , X)," & " 204 (BC_1, * , internal , 0)," & " 205 (BC_4, SPI4_RDAT_12 , input , X)," & " 206 (BC_1, * , internal , 0)," & " 207 (BC_4, SPI4_RDAT_6 , input , X)," & " 208 (BC_1, * , internal , 0)," & " 209 (BC_4, SPI4_RDAT_9 , input , X)," & " 210 (BC_1, * , internal , 0)," & " 211 (BC_4, SPI4_RDAT_3 , input , X)," & " 212 (BC_1, * , internal , 0)," & " 213 (BC_4, SPI4_TCLK_REF , input , X)," & " 214 (BC_1, * , internal , 0)," & " 215 (BC_4, SPI4_RDAT_1 , input , X)," & " 216 (BC_1, * , internal , 0)," & " 217 (BC_4, SPI4_RCTL , input , X)," & " 218 (BC_1, * , internal , 0)," & " 219 (BC_4, SPI4_RDAT_10 , input , X)," & " 220 (BC_1, * , internal , 0)," & " 221 (BC_4, SPI4_RDAT_0 , input , X)," & " 222 (BC_1, * , internal , 0)," & " 223 (BC_4, SPI4_RCLK , input , X)," & " 224 (BC_1, * , internal , 0)," & " 225 (BC_4, SPI4_RDAT_2 , input , X)," & " 226 (BC_1, * , internal , 0)," & " 227 (BC_4, SPI4_RDAT_14 , input , X)," & " 228 (BC_1, * , internal , 0)," & " 229 (BC_4, SPI4_RDAT_4 , input , X)," & " 230 (BC_1, * , internal , 0)," & " 231 (BC_4, SPI4_RDAT_7 , input , X)," & " 232 (BC_1, * , internal , 0)," & " 233 (BC_4, SPI4_RDAT_5 , input , X)," & " 234 (BC_1, * , internal , 0)," & " 235 (BC_4, SPI4_RPROT , input , X)," & " 236 (BC_1, * , internal , 0)," & " 237 (BC_4, SPI4_RPAR , input , X)," & " 238 (BC_1, * , internal , 0)," & " 239 (BC_4, SPI4_RDAT_13 , input , X)," & " 240 (BC_1, * , internal , 0)," & " 241 (BC_4, SPI4_RDAT_15 , input , X)," & " 242 (BC_1, * , internal , 0)," & " 243 (BC_4, SPI4_RDAT_11 , input , X)," & " 244 (BC_1, * , control , 0)," & " 245 (BC_1, SPI4_TDAT_0 , output3 , X, 244, 0, Z)," & " 246 (BC_1, * , control , 0)," & " 247 (BC_1, SPI4_TCTL , output3 , X, 246, 0, Z)," & " 248 (BC_1, * , control , 0)," & " 249 (BC_1, SPI4_TPAR , output3 , X, 248, 0, Z)," & " 250 (BC_1, * , control , 0)," & " 251 (BC_1, SPI4_TPROT , output3 , X, 250, 0, Z)," & " 252 (BC_1, * , control , 0)," & " 253 (BC_1, SPI4_TDAT_13 , output3 , X, 252, 0, Z)," & " 254 (BC_1, * , control , 0)," & " 255 (BC_1, SPI4_TDAT_8 , output3 , X, 254, 0, Z)," & " 256 (BC_1, * , control , 0)," & " 257 (BC_1, SPI4_TDAT_4 , output3 , X, 256, 0, Z)," & " 258 (BC_1, * , control , 0)," & " 259 (BC_1, SPI4_TDAT_12 , output3 , X, 258, 0, Z)," & " 260 (BC_1, * , control , 0)," & " 261 (BC_1, SPI4_RCLK_REF , output3 , X, 260, 0, Z)," & " 262 (BC_1, * , control , 0)," & " 263 (BC_1, SPI4_TDAT_15 , output3 , X, 262, 0, Z)," & " 264 (BC_1, * , control , 0)," & " 265 (BC_1, SPI4_TDAT_1 , output3 , X, 264, 0, Z)," & " 266 (BC_1, * , control , 0)," & " 267 (BC_1, SPI4_TDAT_6 , output3 , X, 266, 0, Z)," & " 268 (BC_1, * , control , 0)," & " 269 (BC_1, SPI4_TDAT_10 , output3 , X, 268, 0, Z)," & " 270 (BC_1, * , control , 0)," & " 271 (BC_1, SPI4_TDAT_11 , output3 , X, 270, 0, Z)," & " 272 (BC_1, * , control , 0)," & " 273 (BC_1, SPI4_TDAT_9 , output3 , X, 272, 0, Z)," & " 274 (BC_1, * , control , 0)," & " 275 (BC_1, SPI4_TCLK , output3 , X, 274, 0, Z)," & " 276 (BC_1, * , control , 0)," & " 277 (BC_1, SPI4_TDAT_14 , output3 , X, 276, 0, Z)," & " 278 (BC_1, * , control , 0)," & " 279 (BC_1, SPI4_TDAT_2 , output3 , X, 278, 0, Z)," & " 280 (BC_1, * , control , 0)," & " 281 (BC_1, SPI4_TDAT_5 , output3 , X, 280, 0, Z)," & " 282 (BC_1, * , control , 0)," & " 283 (BC_1, SPI4_TDAT_3 , output3 , X, 282, 0, Z)," & " 284 (BC_1, * , control , 0)," & " 285 (BC_1, SPI4_TDAT_7 , output3 , X, 284, 0, Z)," & " 286 (BC_1, * , control , 0)," & " 287 (BC_7,SPI4_PREEMP,bidir,X,286,0,Z)," & " 288 (BC_1, * , control , 0)," & " 289 (BC_1, SPI4_TSCLK , output3 , X, 288, 0, Z)," & " 290 (BC_1, * , internal , 0)," & " 291 (BC_4, SPI4_RSTAT_0 , input , X)," & " 292 (BC_1, * , control , 0)," & " 293 (BC_1, SPI4_TSTAT_1 , output3 , X, 292, 0, Z)," & " 294 (BC_1, * , control , 0)," & " 295 (BC_1, SPI4_TSTAT_0 , output3 , X, 294, 0, Z)," & " 296 (BC_1, * , internal , 0)," & " 297 (BC_4, SPI4_RSCLK , input , X)," & " 298 (BC_1, * , internal , 0)," & " 299 (BC_4, SPI4_RSTAT_1 , input , X)," & " 300 (BC_1, * , control , 0)," & " 301 (BC_7,PCI_RST_L,bidir,X,300,0,Z)," & " 302 (BC_1, * , control , 0)," & " 303 (BC_7,PCI_INTA_L,bidir,X,302,0,Z)," & " 304 (BC_1, * , control , 0)," & " 305 (BC_7, PCI_INTB_L, bidir, X,304,0,Z)," & " 306 (BC_1, * , control , 0)," & " 307 (BC_7,PCI_GNT_L_1,bidir,X,306,0,Z)," & " 308 (BC_1, * , control , 0)," & " 309 (BC_7,PCI_GNT_L_0,bidir,X,308,0,Z)," & " 310 (BC_1, * , control , 0)," & " 311 (BC_7, PCI_REQ_L_1, bidir, X,310,0,Z)," & " 312 (BC_1, * , control , 0)," & " 313 (BC_7,PCI_REQ_L_0,bidir,X,312,0,Z)," & " 314 (BC_1, * , control , 0)," & " 315 (BC_7,PCI_AD_29,bidir,X,314,0,Z)," & " 316 (BC_1, * , control , 0)," & " 317 (BC_7,PCI_AD_31,bidir,X,316,0,Z)," & " 318 (BC_1, * , control , 0)," & " 319 (BC_7,PCI_AD_28,bidir,X,318,0,Z)," & " 320 (BC_1, * , control , 0)," & " 321 (BC_7,PCI_AD_30,bidir,X,320,0,Z)," & " 322 (BC_1, * , control , 0)," & " 323 (BC_7,PCI_AD_26,bidir,X,322,0,Z)," & " 324 (BC_1, * , control , 0)," & " 325 (BC_7,PCI_AD_27,bidir,X,324,0,Z)," & " 326 (BC_1, * , control , 0)," & " 327 (BC_7,PCI_CBE_L_3,bidir,X,326,0,Z)," & " 328 (BC_1, * , control , 0)," & " 329 (BC_7,PCI_AD_24,bidir,X,328,0,Z)," & " 330 (BC_1, * , control , 0)," & " 331 (BC_7,PCI_AD_25,bidir,X,330,0,Z)," & " 332 (BC_1, * , control , 0)," & " 333 (BC_7, PCI_IDSEL, bidir, X,332,0,Z)," & " 334 (BC_1, * , control , 0)," & " 335 (BC_7,PCI_AD_22,bidir,X,334,0,Z)," & " 336 (BC_1, * , control , 0)," & " 337 (BC_7,PCI_AD_20,bidir,X,336,0,Z)," & " 338 (BC_1, * , control , 0)," & " 339 (BC_7,PCI_AD_23,bidir,X,338,0,Z)," & " 340 (BC_1, * , control , 0)," & " 341 (BC_7,PCI_AD_21,bidir,X,340,0,Z)," & " 342 (BC_1, * , control , 0)," & " 343 (BC_7,PCI_AD_18,bidir,X,342,0,Z)," & " 344 (BC_1, * , control , 0)," & " 345 (BC_7,PCI_AD_17,bidir,X,344,0,Z)," & " 346 (BC_1, * , control , 0)," & " 347 (BC_7,PCI_FRAME_L,bidir,X,346,0,Z)," & " 348 (BC_1, * , control , 0)," & " 349 (BC_7,PCI_AD_19,bidir,X,348,0,Z)," & " 350 (BC_1, * , control , 0)," & " 351 (BC_7,PCI_IRDY_L,bidir,X,350,0,Z)," & " 352 (BC_1, * , control , 0)," & " 353 (BC_7,PCI_AD_16,bidir,X,352,0,Z)," & " 354 (BC_1, * , control , 0)," & " 355 (BC_7,PCI_DEVSEL_L,bidir,X,354,0,Z)," & " 356 (BC_1, * , control , 0)," & " 357 (BC_7,PCI_CBE_L_2,bidir,X,356,0,Z)," & " 358 (BC_1, * , control , 0)," & " 359 (BC_7,PCI_SERR_L,bidir,X,358,0,Z)," & " 360 (BC_1, * , control , 0)," & " 361 (BC_7,PCI_TRDY_L,bidir,X,360,0,Z)," & " 362 (BC_1, * , control , 0)," & " 363 (BC_7,PCI_PERR_L,bidir,X,362,0,Z)," & " 364 (BC_1, * , control , 0)," & " 365 (BC_7,PCI_PAR,bidir,X,364,0,Z)," & " 366 (BC_1, * , control , 0)," & " 367 (BC_7,PCI_STOP_L,bidir,X,366,0,Z)," & " 368 (BC_1, * , control , 0)," & " 369 (BC_7,PCI_AD_15,bidir,X,368,0,Z)," & " 370 (BC_1, * , control , 0)," & " 371 (BC_7,PCI_CBE_L_1,bidir,X,370,0,Z)," & " 372 (BC_1, * , control , 0)," & " 373 (BC_7,PCI_AD_13,bidir,X,372,0,Z)," & " 374 (BC_1, * , control , 0)," & " 375 (BC_7,PCI_AD_11,bidir,X,374,0,Z)," & " 376 (BC_1, * , control , 0)," & " 377 (BC_7,PCI_AD_14,bidir,X,376,0,Z)," & " 378 (BC_1, * , control , 0)," & " 379 (BC_7,PCI_AD_10,bidir,X,378,0,Z)," & " 380 (BC_1, * , control , 0)," & " 381 (BC_7,PCI_AD_9,bidir,X,380,0,Z)," & " 382 (BC_1, * , control , 0)," & " 383 (BC_7,PCI_AD_12,bidir,X,382,0,Z)," & " 384 (BC_1, * , control , 0)," & " 385 (BC_7,PCI_AD_8,bidir,X,384,0,Z)," & " 386 (BC_1, * , control , 0)," & " 387 (BC_7,PCI_CBE_L_0,bidir,X,386,0,Z)," & " 388 (BC_1, * , control , 0)," & " 389 (BC_7,PCI_AD_7,bidir,X,388,0,Z)," & " 390 (BC_1, * , control , 0)," & " 391 (BC_7,PCI_AD_4,bidir,X,390,0,Z)," & " 392 (BC_1, * , control , 0)," & " 393 (BC_7,PCI_AD_6,bidir,X,392,0,Z)," & " 394 (BC_1, * , control , 0)," & " 395 (BC_7,PCI_AD_5,bidir,X,394,0,Z)," & " 396 (BC_1, * , control , 0)," & " 397 (BC_7,PCI_AD_3,bidir,X,396,0,Z)," & " 398 (BC_1, * , control , 0)," & " 399 (BC_7,PCI_AD_2,bidir,X,398,0,Z)," & " 400 (BC_1, * , control , 0)," & " 401 (BC_7,PCI_AD_0,bidir,X,400,0,Z)," & " 402 (BC_1, * , control , 0)," & " 403 (BC_7,PCI_AD_1,bidir,X,402,0,Z)," & " 404 (BC_1, * , control , 0)," & " 405 (BC_7,PCI_REQ64_L,bidir,X,404,0,Z)," & " 406 (BC_1, * , control , 0)," & " 407 (BC_7,PCI_CBE_L_6,bidir,X,406,0,Z)," & " 408 (BC_1, * , control , 0)," & " 409 (BC_7,PCI_ACK64_L,bidir,X,408,0,Z)," & " 410 (BC_1, * , control , 0)," & " 411 (BC_7,PCI_CBE_L_5,bidir,X,410,0,Z)," & " 412 (BC_1, * , control , 0)," & " 413 (BC_7,PCI_CBE_L_7,bidir,X,412,0,Z)," & " 414 (BC_1, * , control , 0)," & " 415 (BC_7,PCI_AD_63,bidir,X,414,0,Z)," & " 416 (BC_1, * , control , 0)," & " 417 (BC_7,PCI_CBE_L_4,bidir,X,416,0,Z)," & " 418 (BC_1, * , control , 0)," & " 419 (BC_7,PCI_PAR64,bidir,X,418,0,Z)," & " 420 (BC_1, * , control , 0)," & " 421 (BC_7,PCI_AD_62,bidir,X,420,0,Z)," & " 422 (BC_1, * , control , 0)," & " 423 (BC_7,PCI_AD_60,bidir,X,422,0,Z)," & " 424 (BC_1, * , control , 0)," & " 425 (BC_7,PCI_AD_58,bidir,X,424,0,Z)," & " 426 (BC_1, * , control , 0)," & " 427 (BC_7,PCI_AD_61,bidir,X,426,0,Z)," & " 428 (BC_1, * , control , 0)," & " 429 (BC_7,PCI_AD_59,bidir,X,428,0,Z)," & " 430 (BC_1, * , control , 0)," & " 431 (BC_7,PCI_AD_56,bidir,X,430,0,Z)," & " 432 (BC_1, * , control , 0)," & " 433 (BC_7,PCI_AD_57,bidir,X,432,0,Z)," & " 434 (BC_1, * , control , 0)," & " 435 (BC_7,PCI_AD_55,bidir,X,434,0,Z)," & " 436 (BC_1, * , control , 0)," & " 437 (BC_7,PCI_AD_54,bidir,X,436,0,Z)," & " 438 (BC_1, * , control , 0)," & " 439 (BC_7,PCI_AD_52,bidir,X,438,0,Z)," & " 440 (BC_1, * , control , 0)," & " 441 (BC_7,PCI_AD_50,bidir,X,440,0,Z)," & " 442 (BC_1, * , control , 0)," & " 443 (BC_7,PCI_AD_53,bidir,X,442,0,Z)," & " 444 (BC_1, * , control , 0)," & " 445 (BC_7,PCI_AD_49,bidir,X,444,0,Z)," & " 446 (BC_1, * , control , 0)," & " 447 (BC_7,PCI_AD_51,bidir,X,446,0,Z)," & " 448 (BC_1, * , control , 0)," & " 449 (BC_7,PCI_AD_48,bidir,X,448,0,Z)," & " 450 (BC_1, * , control , 0)," & " 451 (BC_7,PCI_AD_46,bidir,X,450,0,Z)," & " 452 (BC_1, * , control , 0)," & " 453 (BC_7,PCI_AD_45,bidir,X,452,0,Z)," & " 454 (BC_1, * , control , 0)," & " 455 (BC_7,PCI_AD_47,bidir,X,454,0,Z)," & " 456 (BC_1, * , control , 0)," & " 457 (BC_7,PCI_AD_43,bidir,X,456,0,Z)," & " 458 (BC_1, * , control , 0)," & " 459 (BC_7,PCI_AD_41,bidir,X,458,0,Z)," & " 460 (BC_1, * , control , 0)," & " 461 (BC_7,PCI_AD_44,bidir,X,460,0,Z)," & " 462 (BC_1, * , control , 0)," & " 463 (BC_7,PCI_AD_40,bidir,X,462,0,Z)," & " 464 (BC_1, * , control , 0)," & " 465 (BC_7,PCI_AD_42,bidir,X,464,0,Z)," & " 466 (BC_1, * , control , 0)," & " 467 (BC_7,PCI_AD_39,bidir,X,466,0,Z)," & " 468 (BC_1, * , control , 0)," & " 469 (BC_7,PCI_AD_37,bidir,X,468,0,Z)," & " 470 (BC_1, * , control , 0)," & " 471 (BC_7,PCI_AD_38,bidir,X,470,0,Z)," & " 472 (BC_1, * , control , 0)," & " 473 (BC_7,PCI_AD_36,bidir,X,472,0,Z)," & " 474 (BC_1, * , control , 0)," & " 475 (BC_7,PCI_AD_35,bidir,X,474,0,Z)," & " 476 (BC_1, * , control , 0)," & " 477 (BC_7,PCI_AD_32,bidir,X,476,0,Z)," & " 478 (BC_1, * , control , 0)," & " 479 (BC_7,PCI_AD_34,bidir,X,478,0,Z)," & " 480 (BC_1, * , control , 0)," & " 481 (BC_7,PCI_AD_33,bidir,X,480,0,Z)," & " 482 (BC_1, * , control , 0)," & " 483 (BC_7, PCI_M66EN, bidir,X,482,0,Z)," & " 484 (BC_1, * , control , 0)," & " 485 (BC_7,RDR0_SCK,bidir,X,484,0,Z)," & " 486 (BC_1, * , control , 0)," & " 487 (BC_7,RDR0_SIO,bidir,X,486,0,Z)," & " 488 (BC_1, * , control , 0)," & " 489 (BC_7,RDR0_CMD,bidir,X,488,0,Z)," & " 490 (BC_1, * , control , 0)," & " 491 (BC_7,RDR0_DQB_8,bidir,X,490,0,Z)," & " 492 (BC_1, * , control , 0)," & " 493 (BC_7,RDR0_DQB_7,bidir,X,492,0,Z)," & " 494 (BC_1, * , control , 0)," & " 495 (BC_7,RDR0_DQB_6,bidir,X,494,0,Z)," & " 496 (BC_1, * , control , 0)," & " 497 (BC_7,RDR0_DQB_5,bidir,X,496,0,Z)," & " 498 (BC_1, * , control , 0)," & " 499 (BC_7,RDR0_DQB_4,bidir,X,498,0,Z)," & " 500 (BC_1, * , control , 0)," & " 501 (BC_7,RDR0_DQB_3,bidir,X,500,0,Z)," & " 502 (BC_1, * , control , 0)," & " 503 (BC_7,RDR0_DQB_2,bidir,X,502,0,Z)," & " 504 (BC_1, * , control , 0)," & " 505 (BC_7,RDR0_DQB_1,bidir,X,504,0,Z)," & " 506 (BC_1, * , control , 0)," & " 507 (BC_7,RDR0_DQB_0,bidir,X,506,0,Z)," & " 508 (BC_1, * , control , 0)," & " 509 (BC_7,RDR0_RQ_0,bidir,X,508,0,Z)," & " 510 (BC_1, * , control , 0)," & " 511 (BC_7,RDR0_RQ_1,bidir,X,510,0,Z)," & " 512 (BC_1, * , control , 0)," & " 513 (BC_7,RDR0_RQ_2,bidir,X,512,0,Z)," & " 514 (BC_1, * , control , 0)," & " 515 (BC_7,RDR0_RQ_3,bidir,X,514,0,Z)," & " 516 (BC_1, * , control , 0)," & " 517 (BC_7,RDR0_RQ_4,bidir,X,516,0,Z)," & " 518 (BC_1, * , control , 0)," & " 519 (BC_7,RDR0_RQ_5,bidir,X,518,0,Z)," & " 520 (BC_1, * , control , 0)," & " 521 (BC_7,RDR0_RQ_6,bidir,X,520,0,Z)," & " 522 (BC_1, * , control , 0)," & " 523 (BC_7,RDR0_RQ_7,bidir,X,522,0,Z)," & " 524 (BC_1, * , control , 0)," & " 525 (BC_7,RDR0_DQA_0,bidir,X,524,0,Z)," & " 526 (BC_1, * , control , 0)," & " 527 (BC_7,RDR0_DQA_1,bidir,X,526,0,Z)," & " 528 (BC_1, * , control , 0)," & " 529 (BC_7,RDR0_DQA_2,bidir,X,528,0,Z)," & " 530 (BC_1, * , control , 0)," & " 531 (BC_7,RDR0_DQA_3,bidir,X,530,0,Z)," & " 532 (BC_1, * , control , 0)," & " 533 (BC_7,RDR0_DQA_4,bidir,X,532,0,Z)," & " 534 (BC_1, * , control , 0)," & " 535 (BC_7,RDR0_DQA_5,bidir,X,534,0,Z)," & " 536 (BC_1, * , control , 0)," & " 537 (BC_7,RDR0_DQA_6,bidir,X,536,0,Z)," & " 538 (BC_1, * , control , 0)," & " 539 (BC_7,RDR0_DQA_7,bidir,X,538,0,Z)," & " 540 (BC_1, * , control , 0)," & " 541 (BC_7,RDR0_DQA_8,bidir,X,540,0,Z)," & " 542 (BC_1, * , control , 0)," & " 543 (BC_7,RDR1_SCK,bidir,X,542,0,Z)," & " 544 (BC_1, * , control , 0)," & " 545 (BC_7,RDR1_SIO,bidir,X,544,0,Z)," & " 546 (BC_1, * , control , 0)," & " 547 (BC_7,RDR1_CMD,bidir,X,546,0,Z)," & " 548 (BC_1, * , control , 0)," & " 549 (BC_7,RDR1_DQB_8,bidir,X,548,0,Z)," & " 550 (BC_1, * , control , 0)," & " 551 (BC_7,RDR1_DQB_7,bidir,X,550,0,Z)," & " 552 (BC_1, * , control , 0)," & " 553 (BC_7,RDR1_DQB_6,bidir,X,552,0,Z)," & " 554 (BC_1, * , control , 0)," & " 555 (BC_7,RDR1_DQB_5,bidir,X,554,0,Z)," & " 556 (BC_1, * , control , 0)," & " 557 (BC_7,RDR1_DQB_4,bidir,X,556,0,Z)," & " 558 (BC_1, * , control , 0)," & " 559 (BC_7,RDR1_DQB_3,bidir,X,558,0,Z)," & " 560 (BC_1, * , control , 0)," & " 561 (BC_7,RDR1_DQB_2,bidir,X,560,0,Z)," & " 562 (BC_1, * , control , 0)," & " 563 (BC_7,RDR1_DQB_1,bidir,X,562,0,Z)," & " 564 (BC_1, * , control , 0)," & " 565 (BC_7,RDR1_DQB_0,bidir,X,564,0,Z)," & " 566 (BC_1, * , control , 0)," & " 567 (BC_7,RDR1_RQ_0,bidir,X,566,0,Z)," & " 568 (BC_1, * , control , 0)," & " 569 (BC_7,RDR1_RQ_1,bidir,X,568,0,Z)," & " 570 (BC_1, * , control , 0)," & " 571 (BC_7,RDR1_RQ_2,bidir,X,570,0,Z)," & " 572 (BC_1, * , control , 0)," & " 573 (BC_7,RDR1_RQ_3,bidir,X,572,0,Z)," & " 574 (BC_1, * , control , 0)," & " 575 (BC_7,RDR1_RQ_4,bidir,X,574,0,Z)," & " 576 (BC_1, * , control , 0)," & " 577 (BC_7,RDR1_RQ_5,bidir,X,576,0,Z)," & " 578 (BC_1, * , control , 0)," & " 579 (BC_7,RDR1_RQ_6,bidir,X,578,0,Z)," & " 580 (BC_1, * , control , 0)," & " 581 (BC_7,RDR1_RQ_7,bidir,X,580,0,Z)," & " 582 (BC_1, * , control , 0)," & " 583 (BC_7,RDR1_DQA_0,bidir,X,582,0,Z)," & " 584 (BC_1, * , control , 0)," & " 585 (BC_7,RDR1_DQA_1,bidir,X,584,0,Z)," & " 586 (BC_1, * , control , 0)," & " 587 (BC_7,RDR1_DQA_2,bidir,X,586,0,Z)," & " 588 (BC_1, * , control , 0)," & " 589 (BC_7,RDR1_DQA_3,bidir,X,588,0,Z)," & " 590 (BC_1, * , control , 0)," & " 591 (BC_7,RDR1_DQA_4,bidir,X,590,0,Z)," & " 592 (BC_1, * , control , 0)," & " 593 (BC_7,RDR1_DQA_5,bidir,X,592,0,Z)," & " 594 (BC_1, * , control , 0)," & " 595 (BC_7,RDR1_DQA_6,bidir,X,594,0,Z)," & " 596 (BC_1, * , control , 0)," & " 597 (BC_7,RDR1_DQA_7,bidir,X,596,0,Z)," & " 598 (BC_1, * , control , 0)," & " 599 (BC_7,RDR1_DQA_8,bidir,X,598,0,Z)," & " 600 (BC_1, * , control , 0)," & " 601 (BC_7,RDR2_SCK,bidir,X,600,0,Z)," & " 602 (BC_1, * , control , 0)," & " 603 (BC_7,RDR2_SIO,bidir,X,602,0,Z)," & " 604 (BC_1, * , control , 0)," & " 605 (BC_7,RDR2_CMD,bidir,X,604,0,Z)," & " 606 (BC_1, * , control , 0)," & " 607 (BC_7,RDR2_DQB_8,bidir,X,606,0,Z)," & " 608 (BC_1, * , control , 0)," & " 609 (BC_7,RDR2_DQB_7,bidir,X,608,0,Z)," & " 610 (BC_1, * , control , 0)," & " 611 (BC_7,RDR2_DQB_6,bidir,X,610,0,Z)," & " 612 (BC_1, * , control , 0)," & " 613 (BC_7,RDR2_DQB_5,bidir,X,612,0,Z)," & " 614 (BC_1, * , control , 0)," & " 615 (BC_7,RDR2_DQB_4,bidir,X,614,0,Z)," & " 616 (BC_1, * , control , 0)," & " 617 (BC_7,RDR2_DQB_3,bidir,X,616,0,Z)," & " 618 (BC_1, * , control , 0)," & " 619 (BC_7,RDR2_DQB_2,bidir,X,618,0,Z)," & " 620 (BC_1, * , control , 0)," & " 621 (BC_7,RDR2_DQB_1,bidir,X,620,0,Z)," & " 622 (BC_1, * , control , 0)," & " 623 (BC_7,RDR2_DQB_0,bidir,X,622,0,Z)," & " 624 (BC_1, * , control , 0)," & " 625 (BC_7,RDR2_RQ_0,bidir,X,624,0,Z)," & " 626 (BC_1, * , control , 0)," & " 627 (BC_7,RDR2_RQ_1,bidir,X,626,0,Z)," & " 628 (BC_1, * , control , 0)," & " 629 (BC_7,RDR2_RQ_2,bidir,X,628,0,Z)," & " 630 (BC_1, * , control , 0)," & " 631 (BC_7,RDR2_RQ_3,bidir,X,630,0,Z)," & " 632 (BC_1, * , control , 0)," & " 633 (BC_7,RDR2_RQ_4,bidir,X,632,0,Z)," & " 634 (BC_1, * , control , 0)," & " 635 (BC_7,RDR2_RQ_5,bidir,X,634,0,Z)," & " 636 (BC_1, * , control , 0)," & " 637 (BC_7,RDR2_RQ_6,bidir,X,636,0,Z)," & " 638 (BC_1, * , control , 0)," & " 639 (BC_7,RDR2_RQ_7,bidir,X,638,0,Z)," & " 640 (BC_1, * , control , 0)," & " 641 (BC_7,RDR2_DQA_0,bidir,X,640,0,Z)," & " 642 (BC_1, * , control , 0)," & " 643 (BC_7,RDR2_DQA_1,bidir,X,642,0,Z)," & " 644 (BC_1, * , control , 0)," & " 645 (BC_7,RDR2_DQA_2,bidir,X,644,0,Z)," & " 646 (BC_1, * , control , 0)," & " 647 (BC_7,RDR2_DQA_3,bidir,X,646,0,Z)," & " 648 (BC_1, * , control , 0)," & " 649 (BC_7,RDR2_DQA_4,bidir,X,648,0,Z)," & " 650 (BC_1, * , control , 0)," & " 651 (BC_7,RDR2_DQA_5,bidir,X,650,0,Z)," & " 652 (BC_1, * , control , 0)," & " 653 (BC_7,RDR2_DQA_6,bidir,X,652,0,Z)," & " 654 (BC_1, * , control , 0)," & " 655 (BC_7,RDR2_DQA_7,bidir,X,654,0,Z)," & " 656 (BC_1, * , control , 0)," & " 657 (BC_7,RDR2_DQA_8,bidir,X,656,0,Z)," & " 658 (BC_1, * , control , 0)," & " 659 (BC_7,GPIO_7,bidir,X,658,0,Z)," & " 660 (BC_1, * , control , 0)," & " 661 (BC_7,GPIO_6,bidir,X,660,0,Z)," & " 662 (BC_1, * , control , 0)," & " 663 (BC_7,GPIO_5,bidir,X,662,0,Z)," & " 664 (BC_1, * , control , 0)," & " 665 (BC_7,GPIO_4,bidir,X,664,0,Z)," & " 666 (BC_1, * , control , 0)," & " 667 (BC_7,GPIO_3,bidir,X,666,0,Z)," & " 668 (BC_1, * , control , 0)," & " 669 (BC_7,GPIO_2,bidir,X,668,0,Z)," & " 670 (BC_1, * , control , 0)," & " 671 (BC_7,GPIO_1,bidir,X,670,0,Z)," & " 672 (BC_1, * , control , 0)," & " 673 (BC_7,GPIO_0,bidir,X,672,0,Z)," & " 674 (BC_1, * , control , 0)," & " 675 (BC_7,SR_TX,bidir,X,674,0,Z)," & " 676 (BC_1, * , control , 0)," & " 677 (BC_7, SR_RX,bidir, X,676,0,Z)," & " 678 (BC_1, * , control , 0)," & " 679 (BC_7,SP_WR_L,bidir,X,678,0,Z)," & " 680 (BC_1, * , control , 0)," & " 681 (BC_7,SP_RD_L,bidir,X,680,0,Z)," & " 682 (BC_1, * , control , 0)," & " 683 (BC_7,SP_AD_0,bidir,X,682,0,Z)," & " 684 (BC_1, * , control , 0)," & " 685 (BC_7,SP_AD_1,bidir,X,684,0,Z)," & " 686 (BC_1, * , control , 0)," & " 687 (BC_7,SP_AD_2,bidir,X,686,0,Z)," & " 688 (BC_1, * , control , 0)," & " 689 (BC_7,SP_AD_3,bidir,X,688,0,Z)," & " 690 (BC_1, * , control , 0)," & " 691 (BC_7,SP_AD_4,bidir,X,690,0,Z)," & " 692 (BC_1, * , control , 0)," & " 693 (BC_7,SP_AD_5,bidir,X,692,0,Z)," & " 694 (BC_1, * , control , 0)," & " 695 (BC_7,SP_AD_6,bidir,X,694,0,Z)," & " 696 (BC_1, * , control , 0)," & " 697 (BC_7,SP_AD_7,bidir,X,696,0,Z)," & " 698 (BC_1, * , control , 0)," & " 699 (BC_7, SP_ACK_L, bidir, X, 698,0,Z)," & " 700 (BC_1, * , control , 0)," & " 701 (BC_7,SP_DIR,bidir,X,700,0,Z)," & " 702 (BC_1, * , control , 0)," & " 703 (BC_7,SP_CLK,bidir,X,702,0,Z)," & " 704 (BC_1, * , control , 0)," & " 705 (BC_7,SP_CS_L_1,bidir,X,704,0,Z)," & " 706 (BC_1, * , control , 0)," & " 707 (BC_7,SP_CS_L_0,bidir,X,706,0,Z)," & " 708 (BC_1, * , control , 0)," & " 709 (BC_7,SP_ALE_L,bidir,X,708,0,Z)," & " 710 (BC_1, * , control , 0)," & " 711 (BC_7,SP_OE_L,bidir,X,710,0,Z)," & " 712 (BC_1, * , control , 0)," & " 713 (BC_7,SP_CP,bidir,X,712,0,Z)," & " 714 (BC_1, * , control , 0)," & " 715 (BC_1, CLK_NRESET_OUT , output3 , X, 714, 0, Z)," & " 716 (BC_1, * , control , 0)," & " 717 (BC_7,QDR3_Q_H_11,bidir,X,716,0,Z)," & " 718 (BC_1, * , control , 0)," & " 719 (BC_7,QDR3_Q_H_8,bidir,X,718,0,Z)," & " 720 (BC_1, * , control , 0)," & " 721 (BC_7,QDR3_Q_H_9,bidir,X,720,0,Z)," & " 722 (BC_1, * , control , 0)," & " 723 (BC_7,QDR3_Q_H_14,bidir,X,722,0,Z)," & " 724 (BC_1, * , control , 0)," & " 725 (BC_7,QDR3_Q_H_6,bidir,X,724,0,Z)," & " 726 (BC_1, * , control , 0)," & " 727 (BC_7,QDR3_Q_H_5,bidir,X,726,0,Z)," & " 728 (BC_1, * , control , 0)," & " 729 (BC_7,QDR3_Q_H_10,bidir,X,728,0,Z)," & " 730 (BC_1, * , control , 0)," & " 731 (BC_7,QDR3_Q_H_12,bidir,X,730,0,Z)," & " 732 (BC_1, * , control , 0)," & " 733 (BC_7,QDR3_Q_H_7,bidir,X,732,0,Z)," & " 734 (BC_1, * , control , 0)," & " 735 (BC_7,QDR3_CIN_H_1,bidir,X,734,0,Z)," & " 736 (BC_1, * , control , 0)," & " 737 (BC_7,QDR3_CIN_L_1,bidir,X,736,0,Z)," & " 738 (BC_1, * , control , 0)," & " 739 (BC_7,QDR3_CIN_L_0,bidir,X,738,0,Z)," & " 740 (BC_1, * , control , 0)," & " 741 (BC_7,QDR3_CIN_H_0,bidir,X,740,0,Z)," & " 742 (BC_1, * , control , 0)," & " 743 (BC_7,QDR3_Q_H_1,bidir,X,742,0,Z)," & " 744 (BC_1, * , control , 0)," & " 745 (BC_7,QDR3_Q_H_3,bidir,X,744,0,Z)," & " 746 (BC_1, * , control , 0)," & " 747 (BC_7,QDR3_Q_H_2,bidir,X,746,0,Z)," & " 748 (BC_1, * , control , 0)," & " 749 (BC_7,QDR3_Q_H_0,bidir,X,748,0,Z)," & " 750 (BC_1, * , control , 0)," & " 751 (BC_7,QDR3_Q_H_16,bidir,X,750,0,Z)," & " 752 (BC_1, * , control , 0)," & " 753 (BC_7,QDR3_Q_H_17,bidir,X,752,0,Z)," & " 754 (BC_1, * , control , 0)," & " 755 (BC_7,QDR3_Q_H_4,bidir,X,754,0,Z)," & " 756 (BC_1, * , control , 0)," & " 757 (BC_7,QDR3_Q_H_15,bidir,X,756,0,Z)," & " 758 (BC_1, * , control , 0)," & " 759 (BC_7,QDR3_Q_H_13,bidir,X,758,0,Z)," & " 760 (BC_1, * , control , 0)," & " 761 (BC_1, QDR3_D_H_10 , output3 , X, 760, 0, Z)," & " 762 (BC_1, * , control , 0)," & " 763 (BC_1, QDR3_D_H_6 , output3 , X, 762, 0, Z)," & " 764 (BC_1, * , control , 0)," & " 765 (BC_1, QDR3_D_H_3 , output3 , X, 764, 0, Z)," & " 766 (BC_1, * , control , 0)," & " 767 (BC_1, QDR3_D_H_5 , output3 , X, 766, 0, Z)," & " 768 (BC_1, * , internal , 0)," & " 769 (BC_1, * , internal , 0)," & " 770 (BC_1, * , control , 0)," & " 771 (BC_1, QDR3_D_H_9 , output3 , X, 770, 0, Z)," & " 772 (BC_1, * , control , 0)," & " 773 (BC_1, QDR3_D_H_8 , output3 , X, 772, 0, Z)," & " 774 (BC_1, * , control , 0)," & " 775 (BC_1, QDR3_D_H_12 , output3 , X, 774, 0, Z)," & " 776 (BC_1, * , control , 0)," & " 777 (BC_1, QDR3_D_H_7 , output3 , X, 776, 0, Z)," & " 778 (BC_1, * , control , 0)," & " 779 (BC_1, QDR3_D_H_11 , output3 , X, 778, 0, Z)," & " 780 (BC_1, * , control , 0)," & " 781 (BC_1, QDR3_D_H_0 , output3 , X, 780, 0, Z)," & " 782 (BC_1, * , control , 0)," & " 783 (BC_1, QDR3_D_H_15 , output3 , X, 782, 0, Z)," & " 784 (BC_1, * , control , 0)," & " 785 (BC_1, QDR3_D_H_4 , output3 , X, 784, 0, Z)," & " 786 (BC_1, * , control , 0)," & " 787 (BC_1, QDR3_D_H_2 , output3 , X, 786, 0, Z)," & " 788 (BC_1, * , control , 0)," & " 789 (BC_1, QDR3_D_H_13 , output3 , X, 788, 0, Z)," & " 790 (BC_1, * , control , 0)," & " 791 (BC_1, QDR3_D_H_14 , output3 , X, 790, 0, Z)," & " 792 (BC_1, * , internal , 0)," & " 793 (BC_1, * , internal , 0)," & " 794 (BC_1, * , control , 0)," & " 795 (BC_1, QDR3_D_H_16 , output3 , X, 794, 0, Z)," & " 796 (BC_1, * , control , 0)," & " 797 (BC_1, QDR3_D_H_1 , output3 , X, 796, 0, Z)," & " 798 (BC_1, * , control , 0)," & " 799 (BC_1, QDR3_D_H_17 , output3 , X, 798, 0, Z)," & " 800 (BC_1, * , control , 0)," & " 801 (BC_1, QDR3_A_H_23 , output3 , X, 800, 0, Z)," & " 802 (BC_1, * , control , 0)," & " 803 (BC_1, QDR3_A_H_21 , output3 , X, 802, 0, Z)," & " 804 (BC_1, * , control , 0)," & " 805 (BC_1, QDR3_A_H_20 , output3 , X, 804, 0, Z)," & " 806 (BC_1, * , control , 0)," & " 807 (BC_1, QDR3_A_H_22 , output3 , X, 806, 0, Z)," & " 808 (BC_1, * , control , 0)," & " 809 (BC_1, QDR3_C_H_0 , output3 , X, 808, 0, Z)," & " 810 (BC_1, * , control , 0)," & " 811 (BC_1, QDR3_C_L_0 , output3 , X, 810, 0, Z)," & " 812 (BC_1, * , control , 0)," & " 813 (BC_1, QDR3_C_L_1 , output3 , X, 812, 0, Z)," & " 814 (BC_1, * , control , 0)," & " 815 (BC_1, QDR3_C_H_1 , output3 , X, 814, 0, Z)," & " 816 (BC_1, * , control , 0)," & " 817 (BC_1, QDR3_WPS_L_0 , output3 , X, 816, 0, Z)," & " 818 (BC_1, * , control , 0)," & " 819 (BC_1, QDR3_BWS_L_1 , output3 , X, 818, 0, Z)," & " 820 (BC_1, * , control , 0)," & " 821 (BC_1, QDR3_RPS_L_0 , output3 , X, 820, 0, Z)," & " 822 (BC_1, * , control , 0)," & " 823 (BC_1, QDR3_RPS_L_1 , output3 , X, 822, 0, Z)," & " 824 (BC_1, * , control , 0)," & " 825 (BC_1, QDR3_WPS_L_1 , output3 , X, 824, 0, Z)," & " 826 (BC_1, * , control , 0)," & " 827 (BC_1, QDR3_A_H_4 , output3 , X, 826, 0, Z)," & " 828 (BC_1, * , control , 0)," & " 829 (BC_1, QDR3_A_H_19 , output3 , X, 828, 0, Z)," & " 830 (BC_1, * , control , 0)," & " 831 (BC_1, QDR3_A_H_3 , output3 , X, 830, 0, Z)," & " 832 (BC_1, * , control , 0)," & " 833 (BC_1, QDR3_A_H_8 , output3 , X, 832, 0, Z)," & " 834 (BC_1, * , control , 0)," & " 835 (BC_1, QDR3_A_H_14 , output3 , X, 834, 0, Z)," & " 836 (BC_1, * , control , 0)," & " 837 (BC_1, QDR3_A_H_11 , output3 , X, 836, 0, Z)," & " 838 (BC_1, * , control , 0)," & " 839 (BC_1, QDR3_A_H_13 , output3 , X, 838, 0, Z)," & " 840 (BC_1, * , internal , 0)," & " 841 (BC_1, * , internal , 0)," & " 842 (BC_1, * , control , 0)," & " 843 (BC_1, QDR3_BWS_L_0 , output3 , X, 842, 0, Z)," & " 844 (BC_1, * , control , 0)," & " 845 (BC_1, QDR3_A_H_9 , output3 , X, 844, 0, Z)," & " 846 (BC_1, * , control , 0)," & " 847 (BC_1, QDR3_A_H_16 , output3 , X, 846, 0, Z)," & " 848 (BC_1, * , control , 0)," & " 849 (BC_1, QDR3_A_H_7 , output3 , X, 848, 0, Z)," & " 850 (BC_1, * , control , 0)," & " 851 (BC_1, QDR3_A_H_0 , output3 , X, 850, 0, Z)," & " 852 (BC_1, * , control , 0)," & " 853 (BC_1, QDR3_A_H_5 , output3 , X, 852, 0, Z)," & " 854 (BC_1, * , control , 0)," & " 855 (BC_1, QDR3_A_H_12 , output3 , X, 854, 0, Z)," & " 856 (BC_1, * , control , 0)," & " 857 (BC_1, QDR3_A_H_10 , output3 , X, 856, 0, Z)," & " 858 (BC_1, * , internal , 0)," & " 859 (BC_1, * , internal , 0)," & " 860 (BC_1, * , control , 0)," & " 861 (BC_1, QDR3_A_H_18 , output3 , X, 860, 0, Z)," & " 862 (BC_1, * , control , 0)," & " 863 (BC_1, QDR3_K_H_1 , output3 , X, 862, 0, Z)," & " 864 (BC_1, * , control , 0)," & " 865 (BC_1, QDR3_K_L_1 , output3 , X, 864, 0, Z)," & " 866 (BC_1, * , control , 0)," & " 867 (BC_1, QDR3_A_H_6 , output3 , X, 866, 0, Z)," & " 868 (BC_1, * , control , 0)," & " 869 (BC_1, QDR3_K_L_0 , output3 , X, 868, 0, Z)," & " 870 (BC_1, * , control , 0)," & " 871 (BC_1, QDR3_K_H_0 , output3 , X, 870, 0, Z)," & " 872 (BC_1, * , control , 0)," & " 873 (BC_1, QDR3_A_H_1 , output3 , X, 872, 0, Z)," & " 874 (BC_1, * , control , 0)," & " 875 (BC_1, QDR3_A_H_17 , output3 , X, 874, 0, Z)," & " 876 (BC_1, * , control , 0)," & " 877 (BC_1, QDR3_A_H_2 , output3 , X, 876, 0, Z)," & " 878 (BC_1, * , control , 0)," & " 879 (BC_1, QDR3_A_H_15 , output3 , X, 878, 0, Z)," & " 880 (BC_1, * , control , 0)," & " 881 (BC_1, QDR2_A_H_19 , output3 , X, 880, 0, Z)," & " 882 (BC_1, * , control , 0)," & " 883 (BC_1, QDR2_A_H_8 , output3 , X, 882, 0, Z)," & " 884 (BC_1, * , control , 0)," & " 885 (BC_1, QDR2_A_H_12 , output3 , X, 884, 0, Z)," & " 886 (BC_1, * , control , 0)," & " 887 (BC_1, QDR2_A_H_16 , output3 , X, 886, 0, Z)," & " 888 (BC_1, * , control , 0)," & " 889 (BC_1, QDR2_K_H_0 , output3 , X, 888, 0, Z)," & " 890 (BC_1, * , control , 0)," & " 891 (B